lsq_unit.hh (3970:d54945bab95d) lsq_unit.hh (4022:c422464ca16e)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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569 load_inst->memData = new uint8_t[64];
570
571 memcpy(load_inst->memData, &data, req->getSize());
572
573 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
574 "addr %#x, data %#x\n",
575 store_idx, req->getVaddr(), data);
576
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 560 unchanged lines hidden (view full) ---

569 load_inst->memData = new uint8_t[64];
570
571 memcpy(load_inst->memData, &data, req->getSize());
572
573 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
574 "addr %#x, data %#x\n",
575 store_idx, req->getVaddr(), data);
576
577 PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
577 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq,
578 Packet::Broadcast);
578 data_pkt->dataStatic(load_inst->memData);
579
580 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
581
582 // We'll say this has a 1 cycle load-store forwarding latency
583 // for now.
584 // @todo: Need to make this a parameter.
585 wb->schedule(curTick);

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633 assert(!load_inst->memData);
634 load_inst->memData = new uint8_t[64];
635
636 ++usedPorts;
637
638 // if we the cache is not blocked, do cache access
639 if (!lsq->cacheBlocked()) {
640 PacketPtr data_pkt =
579 data_pkt->dataStatic(load_inst->memData);
580
581 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
582
583 // We'll say this has a 1 cycle load-store forwarding latency
584 // for now.
585 // @todo: Need to make this a parameter.
586 wb->schedule(curTick);

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634 assert(!load_inst->memData);
635 load_inst->memData = new uint8_t[64];
636
637 ++usedPorts;
638
639 // if we the cache is not blocked, do cache access
640 if (!lsq->cacheBlocked()) {
641 PacketPtr data_pkt =
641 new Packet(req, Packet::ReadReq, Packet::Broadcast);
642 new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
642 data_pkt->dataStatic(load_inst->memData);
643
644 LSQSenderState *state = new LSQSenderState;
645 state->isLoad = true;
646 state->idx = load_idx;
647 state->inst = load_inst;
648 data_pkt->senderState = state;
649

--- 63 unchanged lines hidden --- 		643 data_pkt->dataStatic(load_inst->memData);
644
645 LSQSenderState *state = new LSQSenderState;
646 state->isLoad = true;
647 state->idx = load_idx;
648 state->inst = load_inst;
649 data_pkt->senderState = state;
650

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