lsq_unit.hh (3803:031d9d1b3924) lsq_unit.hh (3876:127c71cfe21a)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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504 int store_idx = load_inst->sqIdx;
505
506 int store_size = 0;
507
508 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
509 "storeHead: %i addr: %#x\n",
510 load_idx, store_idx, storeHead, req->getPaddr());
511
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 495 unchanged lines hidden (view full) ---

504 int store_idx = load_inst->sqIdx;
505
506 int store_size = 0;
507
508 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
509 "storeHead: %i addr: %#x\n",
510 load_idx, store_idx, storeHead, req->getPaddr());
511
512#if FULL_SYSTEM
513 if (req->isLocked()) {
514 // Disable recording the result temporarily. Writing to misc
515 // regs normally updates the result, but this is not the
516 // desired behavior when handling store conditionals.
517 load_inst->recordResult = false;
518 TheISA::handleLockedRead(load_inst.get(), req);
519 load_inst->recordResult = true;
520 }
512 if (req->isLocked()) {
513 // Disable recording the result temporarily. Writing to misc
514 // regs normally updates the result, but this is not the
515 // desired behavior when handling store conditionals.
516 load_inst->recordResult = false;
517 TheISA::handleLockedRead(load_inst.get(), req);
518 load_inst->recordResult = true;
519 }
521#endif
522
523 while (store_idx != -1) {
524 // End once we've reached the top of the LSQ
525 if (store_idx == storeWBIdx) {
526 break;
527 }
528
529 // Move the index to one younger

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556 // Get shift amount for offset into the store's data.
557 int shift_amt = req->getVaddr() & (store_size - 1);
558 // @todo: Magic number, assumes byte addressing
559 shift_amt = shift_amt << 3;
560
561 // Cast this to type T?
562 data = storeQueue[store_idx].data >> shift_amt;
563
520
521 while (store_idx != -1) {
522 // End once we've reached the top of the LSQ
523 if (store_idx == storeWBIdx) {
524 break;
525 }
526
527 // Move the index to one younger

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554 // Get shift amount for offset into the store's data.
555 int shift_amt = req->getVaddr() & (store_size - 1);
556 // @todo: Magic number, assumes byte addressing
557 shift_amt = shift_amt << 3;
558
559 // Cast this to type T?
560 data = storeQueue[store_idx].data >> shift_amt;
561
564 // When the data comes from the store queue entry, it's in host
565 // order. When it gets sent to the load, it needs to be in guest
566 // order so when the load converts it again, it ends up back
567 // in host order like the inst expects.
568 data = TheISA::htog(data);
569
570 assert(!load_inst->memData);
571 load_inst->memData = new uint8_t[64];
572
573 memcpy(load_inst->memData, &data, req->getSize());
574
575 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
576 "addr %#x, data %#x\n",
577 store_idx, req->getVaddr(), data);

--- 137 unchanged lines hidden --- 		562 assert(!load_inst->memData);
563 load_inst->memData = new uint8_t[64];
564
565 memcpy(load_inst->memData, &data, req->getSize());
566
567 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
568 "addr %#x, data %#x\n",
569 store_idx, req->getVaddr(), data);

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