lsq_unit.hh (3349:fec4a86fa212) lsq_unit.hh (3411:07ea0d74b798)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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32#ifndef __CPU_O3_LSQ_UNIT_HH__
33#define __CPU_O3_LSQ_UNIT_HH__
34
35#include <algorithm>
36#include <map>
37#include <queue>
38
39#include "arch/faults.hh"
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 23 unchanged lines hidden (view full) ---

32#ifndef __CPU_O3_LSQ_UNIT_HH__
33#define __CPU_O3_LSQ_UNIT_HH__
34
35#include <algorithm>
36#include <map>
37#include <queue>
38
39#include "arch/faults.hh"
40#include "arch/locked_mem.hh"
40#include "config/full_system.hh"
41#include "base/hashmap.hh"
42#include "cpu/inst_seq.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"
45
46/**
47 * Class that implements the actual LQ and SQ for each specific

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505 int store_size = 0;
506
507 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
508 "storeHead: %i addr: %#x\n",
509 load_idx, store_idx, storeHead, req->getPaddr());
510
511#if FULL_SYSTEM
512 if (req->isLocked()) {
41#include "config/full_system.hh"
42#include "base/hashmap.hh"
43#include "cpu/inst_seq.hh"
44#include "mem/packet.hh"
45#include "mem/port.hh"
46
47/**
48 * Class that implements the actual LQ and SQ for each specific

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506 int store_size = 0;
507
508 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
509 "storeHead: %i addr: %#x\n",
510 load_idx, store_idx, storeHead, req->getPaddr());
511
512#if FULL_SYSTEM
513 if (req->isLocked()) {
513 cpu->lockAddr = req->getPaddr();
514 cpu->lockFlag = true;
514 // Disable recording the result temporarily. Writing to misc
515 // regs normally updates the result, but this is not the
516 // desired behavior when handling store conditionals.
517 load_inst->recordResult = false;
518 TheISA::handleLockedRead(load_inst.get(), req);
519 load_inst->recordResult = true;
515 }
516#endif
517
518 while (store_idx != -1) {
519 // End once we've reached the top of the LSQ
520 if (store_idx == storeWBIdx) {
521 break;
522 }

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521#endif
522
523 while (store_idx != -1) {
524 // End once we've reached the top of the LSQ
525 if (store_idx == storeWBIdx) {
526 break;
527 }

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