lsq_unit.hh (3172:2c84db071850) lsq_unit.hh (3221:669a04468c0d)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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487 assert(load_inst);
488
489 assert(!load_inst->isExecuted());
490
491 // Make sure this isn't an uncacheable access
492 // A bit of a hackish way to get uncached accesses to work only if they're
493 // at the head of the LSQ and are ready to commit (at the head of the ROB
494 // too).
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 478 unchanged lines hidden (view full) ---

487 assert(load_inst);
488
489 assert(!load_inst->isExecuted());
490
491 // Make sure this isn't an uncacheable access
492 // A bit of a hackish way to get uncached accesses to work only if they're
493 // at the head of the LSQ and are ready to commit (at the head of the ROB
494 // too).
495 if (req->isUncacheable() &&
495 if (req->getFlags() & UNCACHEABLE &&
496 (load_idx != loadHead || !load_inst->isAtCommit())) {
497 iewStage->rescheduleMemInst(load_inst);
498 ++lsqRescheduledLoads;
499 return TheISA::genMachineCheckFault();
500 }
501
502 // Check the SQ for any previous stores that might lead to forwarding
503 int store_idx = load_inst->sqIdx;
504
505 int store_size = 0;
506
507 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
508 "storeHead: %i addr: %#x\n",
509 load_idx, store_idx, storeHead, req->getPaddr());
510
511#if FULL_SYSTEM
496 (load_idx != loadHead || !load_inst->isAtCommit())) {
497 iewStage->rescheduleMemInst(load_inst);
498 ++lsqRescheduledLoads;
499 return TheISA::genMachineCheckFault();
500 }
501
502 // Check the SQ for any previous stores that might lead to forwarding
503 int store_idx = load_inst->sqIdx;
504
505 int store_size = 0;
506
507 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
508 "storeHead: %i addr: %#x\n",
509 load_idx, store_idx, storeHead, req->getPaddr());
510
511#if FULL_SYSTEM
512 if (req->isLocked()) {
512 if (req->getFlags() & LOCKED) {
513 cpu->lockAddr = req->getPaddr();
514 cpu->lockFlag = true;
515 }
516#endif
517
518 while (store_idx != -1) {
519 // End once we've reached the top of the LSQ
520 if (store_idx == storeWBIdx) {

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633 state->isLoad = true;
634 state->idx = load_idx;
635 state->inst = load_inst;
636 data_pkt->senderState = state;
637
638 // if we the cache is not blocked, do cache access
639 if (!lsq->cacheBlocked()) {
640 if (!dcachePort->sendTiming(data_pkt)) {
513 cpu->lockAddr = req->getPaddr();
514 cpu->lockFlag = true;
515 }
516#endif
517
518 while (store_idx != -1) {
519 // End once we've reached the top of the LSQ
520 if (store_idx == storeWBIdx) {

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633 state->isLoad = true;
634 state->idx = load_idx;
635 state->inst = load_inst;
636 data_pkt->senderState = state;
637
638 // if we the cache is not blocked, do cache access
639 if (!lsq->cacheBlocked()) {
640 if (!dcachePort->sendTiming(data_pkt)) {
641 if (data_pkt->result == Packet::BadAddress) {
642 delete data_pkt;
643 return TheISA::genMachineCheckFault();
644 }
645
641 // If the access didn't succeed, tell the LSQ by setting
642 // the retry thread id.
643 lsq->setRetryTid(lsqID);
644 }
645 }
646
647 // If the cache was blocked, or has become blocked due to the access,
648 // handle it.

--- 53 unchanged lines hidden --- 		646 // If the access didn't succeed, tell the LSQ by setting
647 // the retry thread id.
648 lsq->setRetryTid(lsqID);
649 }
650 }
651
652 // If the cache was blocked, or has become blocked due to the access,
653 // handle it.

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