lsq_unit.hh (3014:b4309193255a) lsq_unit.hh (3125:febd811bccc6)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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402 InstSeqNum blockedLoadSeqNum;
403
404 /** The oldest load that caused a memory ordering violation. */
405 DynInstPtr memDepViolator;
406
407 // Will also need how many read/write ports the Dcache has. Or keep track
408 // of that in stage that is one level up, and only call executeLoad/Store
409 // the appropriate number of times.
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 393 unchanged lines hidden (view full) ---

402 InstSeqNum blockedLoadSeqNum;
403
404 /** The oldest load that caused a memory ordering violation. */
405 DynInstPtr memDepViolator;
406
407 // Will also need how many read/write ports the Dcache has. Or keep track
408 // of that in stage that is one level up, and only call executeLoad/Store
409 // the appropriate number of times.
410
411 /** Total number of loads forwaded from LSQ stores. */
412 Stats::Scalar<> lsqForwLoads;
413
410 /** Total number of loads forwaded from LSQ stores. */
411 Stats::Scalar<> lsqForwLoads;
412
414 /** Total number of loads ignored due to invalid addresses. */
415 Stats::Scalar<> invAddrLoads;
416
417 /** Total number of squashed loads. */
418 Stats::Scalar<> lsqSquashedLoads;
419
420 /** Total number of responses from the memory system that are
421 * ignored due to the instruction already being squashed. */
422 Stats::Scalar<> lsqIgnoredResponses;
423
424 /** Total number of squashed stores. */
425 Stats::Scalar<> lsqSquashedStores;
426
427 /** Total number of software prefetches ignored due to invalid addresses. */
428 Stats::Scalar<> invAddrSwpfs;
429
430 /** Ready loads blocked due to partial store-forwarding. */
431 Stats::Scalar<> lsqBlockedLoads;

--- 268 unchanged lines hidden --- 		413 /** Total number of squashed stores. */
414 Stats::Scalar<> lsqSquashedStores;
415
416 /** Total number of software prefetches ignored due to invalid addresses. */
417 Stats::Scalar<> invAddrSwpfs;
418
419 /** Ready loads blocked due to partial store-forwarding. */
420 Stats::Scalar<> lsqBlockedLoads;

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