lsq_unit.hh (2907:7b0ababb4166) lsq_unit.hh (2927:62f1518ae800)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 587 unchanged lines hidden (view full) ---

596 stalled = true;
597 stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
598 stallingLoadIdx = load_idx;
599 }
600
601 // Tell IQ/mem dep unit that this instruction will need to be
602 // rescheduled eventually
603 iewStage->rescheduleMemInst(load_inst);
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 587 unchanged lines hidden (view full) ---

596 stalled = true;
597 stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
598 stallingLoadIdx = load_idx;
599 }
600
601 // Tell IQ/mem dep unit that this instruction will need to be
602 // rescheduled eventually
603 iewStage->rescheduleMemInst(load_inst);
604 iewStage->decrWb(load_inst->seqNum);
604 ++lsqRescheduledLoads;
605
606 // Do not generate a writeback event as this instruction is not
607 // complete.
608 DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
609 "Store idx %i to load addr %#x\n",
610 store_idx, req->getVaddr());
611

--- 85 unchanged lines hidden --- 		605 ++lsqRescheduledLoads;
606
607 // Do not generate a writeback event as this instruction is not
608 // complete.
609 DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
610 "Store idx %i to load addr %#x\n",
611 store_idx, req->getVaddr());
612

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