lsq_unit.hh (2693:18c6be231eb1) lsq_unit.hh (2698:d5f35d41e017)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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37#include <queue>
38
39#include "arch/faults.hh"
40#include "config/full_system.hh"
41#include "base/hashmap.hh"
42#include "cpu/inst_seq.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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37#include <queue>
38
39#include "arch/faults.hh"
40#include "config/full_system.hh"
41#include "base/hashmap.hh"
42#include "cpu/inst_seq.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"
45//#include "mem/page_table.hh"
46//#include "sim/debug.hh"
47//#include "sim/sim_object.hh"
48
49/**
50 * Class that implements the actual LQ and SQ for each specific
51 * thread. Both are circular queues; load entries are freed upon
52 * committing, while store entries are freed once they writeback. The
53 * LSQUnit tracks if there are memory ordering violations, and also
54 * detects partial load to store forwarding cases (a store only has
55 * part of a load's data) that requires the load to wait until the

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82
83 /** Sets the CPU pointer. */
84 void setCPU(FullCPU *cpu_ptr);
85
86 /** Sets the IEW stage pointer. */
87 void setIEW(IEW *iew_ptr)
88 { iewStage = iew_ptr; }
89
45
46/**
47 * Class that implements the actual LQ and SQ for each specific
48 * thread. Both are circular queues; load entries are freed upon
49 * committing, while store entries are freed once they writeback. The
50 * LSQUnit tracks if there are memory ordering violations, and also
51 * detects partial load to store forwarding cases (a store only has
52 * part of a load's data) that requires the load to wait until the

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79
80 /** Sets the CPU pointer. */
81 void setCPU(FullCPU *cpu_ptr);
82
83 /** Sets the IEW stage pointer. */
84 void setIEW(IEW *iew_ptr)
85 { iewStage = iew_ptr; }
86
90 /** Sets the page table pointer. */
91// void setPageTable(PageTable *pt_ptr);
92
93 /** Switches out LSQ unit. */
94 void switchOut();
95
96 /** Takes over from another CPU's thread. */
97 void takeOverFrom();
98
99 /** Returns if the LSQ is switched out. */
100 bool isSwitchedOut() { return switchedOut; }

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206 int numStoresToWB() { return storesToWB; }
207
208 /** Returns if the LSQ unit will writeback on this cycle. */
209 bool willWB() { return storeQueue[storeWBIdx].canWB &&
210 !storeQueue[storeWBIdx].completed &&
211 !isStoreBlocked; }
212
213 private:
87 /** Switches out LSQ unit. */
88 void switchOut();
89
90 /** Takes over from another CPU's thread. */
91 void takeOverFrom();
92
93 /** Returns if the LSQ is switched out. */
94 bool isSwitchedOut() { return switchedOut; }

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200 int numStoresToWB() { return storesToWB; }
201
202 /** Returns if the LSQ unit will writeback on this cycle. */
203 bool willWB() { return storeQueue[storeWBIdx].canWB &&
204 !storeQueue[storeWBIdx].completed &&
205 !isStoreBlocked; }
206
207 private:
208 /** Writes back the instruction, sending it to IEW. */
214 void writeback(DynInstPtr &inst, PacketPtr pkt);
215
209 void writeback(DynInstPtr &inst, PacketPtr pkt);
210
211 /** Handles completing the send of a store to memory. */
216 void storePostSend(Packet *pkt);
217
218 /** Completes the store at the specified index. */
219 void completeStore(int store_idx);
220
221 /** Handles doing the retry. */
222 void recvRetry();
223

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236
237 private:
238 /** Pointer to the CPU. */
239 FullCPU *cpu;
240
241 /** Pointer to the IEW stage. */
242 IEW *iewStage;
243
212 void storePostSend(Packet *pkt);
213
214 /** Completes the store at the specified index. */
215 void completeStore(int store_idx);
216
217 /** Handles doing the retry. */
218 void recvRetry();
219

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232
233 private:
234 /** Pointer to the CPU. */
235 FullCPU *cpu;
236
237 /** Pointer to the IEW stage. */
238 IEW *iewStage;
239
240 /** Pointer to memory object. */
244 MemObject *mem;
245
241 MemObject *mem;
242
243 /** DcachePort class for this LSQ Unit. Handles doing the
244 * communication with the cache/memory.
245 * @todo: Needs to be moved to the LSQ level and have some sort
246 * of arbitration.
247 */
246 class DcachePort : public Port
247 {
248 protected:
248 class DcachePort : public Port
249 {
250 protected:
251 /** Pointer to CPU. */
249 FullCPU *cpu;
252 FullCPU *cpu;
253 /** Pointer to LSQ. */
250 LSQUnit *lsq;
251
252 public:
254 LSQUnit *lsq;
255
256 public:
257 /** Default constructor. */
253 DcachePort(FullCPU *_cpu, LSQUnit *_lsq)
254 : Port(_lsq->name() + "-dport"), cpu(_cpu), lsq(_lsq)
255 { }
256
257 protected:
258 DcachePort(FullCPU *_cpu, LSQUnit *_lsq)
259 : Port(_lsq->name() + "-dport"), cpu(_cpu), lsq(_lsq)
260 { }
261
262 protected:
263 /** Atomic version of receive. Panics. */
258 virtual Tick recvAtomic(PacketPtr pkt);
259
264 virtual Tick recvAtomic(PacketPtr pkt);
265
266 /** Functional version of receive. Panics. */
260 virtual void recvFunctional(PacketPtr pkt);
261
267 virtual void recvFunctional(PacketPtr pkt);
268
269 /** Receives status change. Other than range changing, panics. */
262 virtual void recvStatusChange(Status status);
263
270 virtual void recvStatusChange(Status status);
271
272 /** Returns the address ranges of this device. */
264 virtual void getDeviceAddressRanges(AddrRangeList &resp,
265 AddrRangeList &snoop)
266 { resp.clear(); snoop.clear(); }
267
273 virtual void getDeviceAddressRanges(AddrRangeList &resp,
274 AddrRangeList &snoop)
275 { resp.clear(); snoop.clear(); }
276
277 /** Timing version of receive. Handles writing back and
278 * completing the load or store that has returned from
279 * memory. */
268 virtual bool recvTiming(PacketPtr pkt);
269
280 virtual bool recvTiming(PacketPtr pkt);
281
282 /** Handles doing a retry of the previous send. */
270 virtual void recvRetry();
271 };
272
273 /** Pointer to the D-cache. */
274 DcachePort *dcachePort;
275
283 virtual void recvRetry();
284 };
285
286 /** Pointer to the D-cache. */
287 DcachePort *dcachePort;
288
289 /** Derived class to hold any sender state the LSQ needs. */
276 class LSQSenderState : public Packet::SenderState
277 {
278 public:
290 class LSQSenderState : public Packet::SenderState
291 {
292 public:
293 /** Default constructor. */
279 LSQSenderState()
280 : noWB(false)
281 { }
282
294 LSQSenderState()
295 : noWB(false)
296 { }
297
283// protected:
298 /** Instruction who initiated the access to memory. */
284 DynInstPtr inst;
299 DynInstPtr inst;
300 /** Whether or not it is a load. */
285 bool isLoad;
301 bool isLoad;
302 /** The LQ/SQ index of the instruction. */
286 int idx;
303 int idx;
304 /** Whether or not the instruction will need to writeback. */
287 bool noWB;
288 };
289
305 bool noWB;
306 };
307
290 /** Pointer to the page table. */
291// PageTable *pTable;
292
308 /** Writeback event, specifically for when stores forward data to loads. */
293 class WritebackEvent : public Event {
294 public:
295 /** Constructs a writeback event. */
296 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr);
297
298 /** Processes the writeback event. */
299 void process();
300
301 /** Returns the description of this event. */
302 const char *description();
303
304 private:
309 class WritebackEvent : public Event {
310 public:
311 /** Constructs a writeback event. */
312 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr);
313
314 /** Processes the writeback event. */
315 void process();
316
317 /** Returns the description of this event. */
318 const char *description();
319
320 private:
321 /** Instruction whose results are being written back. */
305 DynInstPtr inst;
306
322 DynInstPtr inst;
323
324 /** The packet that would have been sent to memory. */
307 PacketPtr pkt;
308
309 /** The pointer to the LSQ unit that issued the store. */
310 LSQUnit<Impl> *lsqPtr;
311 };
312
313 public:
314 struct SQEntry {

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399 bool stalled;
400 /** The store that causes the stall due to partial store to load
401 * forwarding.
402 */
403 InstSeqNum stallingStoreIsn;
404 /** The index of the above store. */
405 int stallingLoadIdx;
406
325 PacketPtr pkt;
326
327 /** The pointer to the LSQ unit that issued the store. */
328 LSQUnit<Impl> *lsqPtr;
329 };
330
331 public:
332 struct SQEntry {

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417 bool stalled;
418 /** The store that causes the stall due to partial store to load
419 * forwarding.
420 */
421 InstSeqNum stallingStoreIsn;
422 /** The index of the above store. */
423 int stallingLoadIdx;
424
407 PacketPtr sendingPkt;
425 /** The packet that needs to be retried. */
426 PacketPtr retryPkt;
408
427
428 /** Whehter or not a store is blocked due to the memory system. */
409 bool isStoreBlocked;
410
411 /** Whether or not a load is blocked due to the memory system. */
412 bool isLoadBlocked;
413
414 /** Has the blocked load been handled. */
415 bool loadBlockedHandled;
416

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430
431 /** Whether or not a load is blocked due to the memory system. */
432 bool isLoadBlocked;
433
434 /** Has the blocked load been handled. */
435 bool loadBlockedHandled;
436

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