lsq_unit.hh (2674:6d4afef73a20) lsq_unit.hh (2678:1f86b91dc3bb)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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125 /** Commits stores older than a specific sequence number. */
126 void commitStores(InstSeqNum &youngest_inst);
127
128 /** Writes back stores. */
129 void writebackStores();
130
131 void completeDataAccess(PacketPtr pkt);
132
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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125 /** Commits stores older than a specific sequence number. */
126 void commitStores(InstSeqNum &youngest_inst);
127
128 /** Writes back stores. */
129 void writebackStores();
130
131 void completeDataAccess(PacketPtr pkt);
132
133 void completeStoreDataAccess(DynInstPtr &inst);
134
135 // @todo: Include stats in the LSQ unit.
136 //void regStats();
137
138 /** Clears all the entries in the LQ. */
139 void clearLQ();
140
141 /** Clears all the entries in the SQ. */
142 void clearSQ();

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201 /** Returns if there are any stores to writeback. */
202 bool hasStoresToWB() { return storesToWB; }
203
204 /** Returns the number of stores to writeback. */
205 int numStoresToWB() { return storesToWB; }
206
207 /** Returns if the LSQ unit will writeback on this cycle. */
208 bool willWB() { return storeQueue[storeWBIdx].canWB &&
133 // @todo: Include stats in the LSQ unit.
134 //void regStats();
135
136 /** Clears all the entries in the LQ. */
137 void clearLQ();
138
139 /** Clears all the entries in the SQ. */
140 void clearSQ();

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199 /** Returns if there are any stores to writeback. */
200 bool hasStoresToWB() { return storesToWB; }
201
202 /** Returns the number of stores to writeback. */
203 int numStoresToWB() { return storesToWB; }
204
205 /** Returns if the LSQ unit will writeback on this cycle. */
206 bool willWB() { return storeQueue[storeWBIdx].canWB &&
209 !storeQueue[storeWBIdx].completed/* &&
210 !dcacheInterface->isBlocked()*/; }
207 !storeQueue[storeWBIdx].completed &&
208 !isStoreBlocked; }
211
212 private:
209
210 private:
211 void writeback(DynInstPtr &inst, PacketPtr pkt);
212
213 /** Completes the store at the specified index. */
214 void completeStore(int store_idx);
215
216 /** Increments the given store index (circular queue). */
217 inline void incrStIdx(int &store_idx);
218 /** Decrements the given store index (circular queue). */
219 inline void decrStIdx(int &store_idx);
220 /** Increments the given load index (circular queue). */

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260 virtual bool recvTiming(PacketPtr pkt);
261
262 virtual void recvRetry();
263 };
264
265 /** Pointer to the D-cache. */
266 DcachePort *dcachePort;
267
213 /** Completes the store at the specified index. */
214 void completeStore(int store_idx);
215
216 /** Increments the given store index (circular queue). */
217 inline void incrStIdx(int &store_idx);
218 /** Decrements the given store index (circular queue). */
219 inline void decrStIdx(int &store_idx);
220 /** Increments the given load index (circular queue). */

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260 virtual bool recvTiming(PacketPtr pkt);
261
262 virtual void recvRetry();
263 };
264
265 /** Pointer to the D-cache. */
266 DcachePort *dcachePort;
267
268 class LSQSenderState : public Packet::SenderState
269 {
270 public:
271 LSQSenderState()
272 : noWB(false)
273 { }
274
275// protected:
276 DynInstPtr inst;
277 bool isLoad;
278 int idx;
279 bool noWB;
280 };
281
268 /** Pointer to the page table. */
269// PageTable *pTable;
270
282 /** Pointer to the page table. */
283// PageTable *pTable;
284
285 class WritebackEvent : public Event {
286 public:
287 /** Constructs a writeback event. */
288 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr);
289
290 /** Processes the writeback event. */
291 void process();
292
293 /** Returns the description of this event. */
294 const char *description();
295
296 private:
297 DynInstPtr inst;
298
299 PacketPtr pkt;
300
301 /** The pointer to the LSQ unit that issued the store. */
302 LSQUnit<Impl> *lsqPtr;
303 };
304
271 public:
272 struct SQEntry {
273 /** Constructs an empty store queue entry. */
274 SQEntry()
275 : inst(NULL), req(NULL), size(0), data(0),
276 canWB(0), committed(0), completed(0)
277 { }
278

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357 bool stalled;
358 /** The store that causes the stall due to partial store to load
359 * forwarding.
360 */
361 InstSeqNum stallingStoreIsn;
362 /** The index of the above store. */
363 int stallingLoadIdx;
364
305 public:
306 struct SQEntry {
307 /** Constructs an empty store queue entry. */
308 SQEntry()
309 : inst(NULL), req(NULL), size(0), data(0),
310 canWB(0), committed(0), completed(0)
311 { }
312

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391 bool stalled;
392 /** The store that causes the stall due to partial store to load
393 * forwarding.
394 */
395 InstSeqNum stallingStoreIsn;
396 /** The index of the above store. */
397 int stallingLoadIdx;
398
399 bool isStoreBlocked;
400
365 /** Whether or not a load is blocked due to the memory system. */
366 bool isLoadBlocked;
367
368 /** Has the blocked load been handled. */
369 bool loadBlockedHandled;
370
371 /** The sequence number of the blocked load. */
372 InstSeqNum blockedLoadSeqNum;

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516 assert(!load_inst->memData);
517 load_inst->memData = new uint8_t[64];
518
519 memcpy(load_inst->memData, &data, req->getSize());
520
521 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
522 "addr %#x, data %#x\n",
523 store_idx, req->getVaddr(), *(load_inst->memData));
401 /** Whether or not a load is blocked due to the memory system. */
402 bool isLoadBlocked;
403
404 /** Has the blocked load been handled. */
405 bool loadBlockedHandled;
406
407 /** The sequence number of the blocked load. */
408 InstSeqNum blockedLoadSeqNum;

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552 assert(!load_inst->memData);
553 load_inst->memData = new uint8_t[64];
554
555 memcpy(load_inst->memData, &data, req->getSize());
556
557 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
558 "addr %#x, data %#x\n",
559 store_idx, req->getVaddr(), *(load_inst->memData));
524/*
525 typename LdWritebackEvent *wb =
526 new typename LdWritebackEvent(load_inst,
527 iewStage);
528
560
561 PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
562 data_pkt->dataStatic(load_inst->memData);
563
564 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
565
529 // We'll say this has a 1 cycle load-store forwarding latency
530 // for now.
531 // @todo: Need to make this a parameter.
532 wb->schedule(curTick);
566 // We'll say this has a 1 cycle load-store forwarding latency
567 // for now.
568 // @todo: Need to make this a parameter.
569 wb->schedule(curTick);
533*/
570
534 // Should keep track of stat for forwarded data
535 return NoFault;
536 } else if ((store_has_lower_limit && lower_load_has_store_part) ||
537 (store_has_upper_limit && upper_load_has_store_part) ||
538 (lower_load_has_store_part && upper_load_has_store_part)) {
539 // This is the partial store-load forwarding case where a store
540 // has only part of the load's data.
541

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580 ++usedPorts;
581
582 DPRINTF(LSQUnit, "Doing timing access for inst PC %#x\n",
583 load_inst->readPC());
584
585 PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
586 data_pkt->dataStatic(load_inst->memData);
587
571 // Should keep track of stat for forwarded data
572 return NoFault;
573 } else if ((store_has_lower_limit && lower_load_has_store_part) ||
574 (store_has_upper_limit && upper_load_has_store_part) ||
575 (lower_load_has_store_part && upper_load_has_store_part)) {
576 // This is the partial store-load forwarding case where a store
577 // has only part of the load's data.
578

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617 ++usedPorts;
618
619 DPRINTF(LSQUnit, "Doing timing access for inst PC %#x\n",
620 load_inst->readPC());
621
622 PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
623 data_pkt->dataStatic(load_inst->memData);
624
625 LSQSenderState *state = new LSQSenderState;
626 state->isLoad = true;
627 state->idx = load_idx;
628 state->inst = load_inst;
629 data_pkt->senderState = state;
630
588 // if we have a cache, do cache access too
589 if (!dcachePort->sendTiming(data_pkt)) {
590 // There's an older load that's already going to squash.
591 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
592 return NoFault;
593
594 // Record that the load was blocked due to memory. This
595 // load will squash all instructions after it, be

--- 43 unchanged lines hidden --- 		631 // if we have a cache, do cache access too
632 if (!dcachePort->sendTiming(data_pkt)) {
633 // There's an older load that's already going to squash.
634 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
635 return NoFault;
636
637 // Record that the load was blocked due to memory. This
638 // load will squash all instructions after it, be

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