lsq_unit.hh (14030:a58e14bf581c) lsq_unit.hh (14083:057fe59ed45a)
1/*
2 * Copyright (c) 2012-2014,2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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662
663 if (req->mainRequest()->isMmappedIpr()) {
664 assert(!load_inst->memData);
665 load_inst->memData = new uint8_t[MaxDataBytes];
666
667 ThreadContext *thread = cpu->tcBase(lsqID);
668 PacketPtr main_pkt = new Packet(req->mainRequest(), MemCmd::ReadReq);
669
1/*
2 * Copyright (c) 2012-2014,2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 653 unchanged lines hidden (view full) ---

662
663 if (req->mainRequest()->isMmappedIpr()) {
664 assert(!load_inst->memData);
665 load_inst->memData = new uint8_t[MaxDataBytes];
666
667 ThreadContext *thread = cpu->tcBase(lsqID);
668 PacketPtr main_pkt = new Packet(req->mainRequest(), MemCmd::ReadReq);
669
670 main_pkt->dataStatic(load_inst->memData);
671
670 Cycles delay = req->handleIprRead(thread, main_pkt);
671
672 WritebackEvent *wb = new WritebackEvent(load_inst, main_pkt, this);
673 cpu->schedule(wb, cpu->clockEdge(delay));
674 return NoFault;
675 }
676
677 // Check the SQ for any previous stores that might lead to forwarding

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672 Cycles delay = req->handleIprRead(thread, main_pkt);
673
674 WritebackEvent *wb = new WritebackEvent(load_inst, main_pkt, this);
675 cpu->schedule(wb, cpu->clockEdge(delay));
676 return NoFault;
677 }
678
679 // Check the SQ for any previous stores that might lead to forwarding

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