lsq_unit.hh (12749:223c83ed9979) lsq_unit.hh (13429:a1e199fd8122)
1/*
2 * Copyright (c) 2012-2014,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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111 /** Ticks the LSQ unit, which in this case only resets the number of
112 * used cache ports.
113 * @todo: Move the number of used ports up to the LSQ level so it can
114 * be shared by all LSQ units.
115 */
116 void tick() { usedStorePorts = 0; }
117
118 /** Inserts an instruction. */
1/*
2 * Copyright (c) 2012-2014,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 102 unchanged lines hidden (view full) ---

111 /** Ticks the LSQ unit, which in this case only resets the number of
112 * used cache ports.
113 * @todo: Move the number of used ports up to the LSQ level so it can
114 * be shared by all LSQ units.
115 */
116 void tick() { usedStorePorts = 0; }
117
118 /** Inserts an instruction. */
119 void insert(DynInstPtr &inst);
119 void insert(const DynInstPtr &inst);
120 /** Inserts a load instruction. */
120 /** Inserts a load instruction. */
121 void insertLoad(DynInstPtr &load_inst);
121 void insertLoad(const DynInstPtr &load_inst);
122 /** Inserts a store instruction. */
122 /** Inserts a store instruction. */
123 void insertStore(DynInstPtr &store_inst);
123 void insertStore(const DynInstPtr &store_inst);
124
125 /** Check for ordering violations in the LSQ. For a store squash if we
126 * ever find a conflicting load. For a load, only squash if we
127 * an external snoop invalidate has been seen for that load address
128 * @param load_idx index to start checking at
129 * @param inst the instruction to check
130 */
124
125 /** Check for ordering violations in the LSQ. For a store squash if we
126 * ever find a conflicting load. For a load, only squash if we
127 * an external snoop invalidate has been seen for that load address
128 * @param load_idx index to start checking at
129 * @param inst the instruction to check
130 */
131 Fault checkViolations(int load_idx, DynInstPtr &inst);
131 Fault checkViolations(int load_idx, const DynInstPtr &inst);
132
133 /** Check if an incoming invalidate hits in the lsq on a load
134 * that might have issued out of order wrt another load beacuse
135 * of the intermediate invalidate.
136 */
137 void checkSnoop(PacketPtr pkt);
138
139 /** Executes a load instruction. */
132
133 /** Check if an incoming invalidate hits in the lsq on a load
134 * that might have issued out of order wrt another load beacuse
135 * of the intermediate invalidate.
136 */
137 void checkSnoop(PacketPtr pkt);
138
139 /** Executes a load instruction. */
140 Fault executeLoad(DynInstPtr &inst);
140 Fault executeLoad(const DynInstPtr &inst);
141
142 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
143 /** Executes a store instruction. */
141
142 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
143 /** Executes a store instruction. */
144 Fault executeStore(DynInstPtr &inst);
144 Fault executeStore(const DynInstPtr &inst);
145
146 /** Commits the head load. */
147 void commitLoad();
148 /** Commits loads older than a specific sequence number. */
149 void commitLoads(InstSeqNum &youngest_inst);
150
151 /** Commits stores older than a specific sequence number. */
152 void commitStores(InstSeqNum &youngest_inst);

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228 /** Handles doing the retry. */
229 void recvRetry();
230
231 private:
232 /** Reset the LSQ state */
233 void resetState();
234
235 /** Writes back the instruction, sending it to IEW. */
145
146 /** Commits the head load. */
147 void commitLoad();
148 /** Commits loads older than a specific sequence number. */
149 void commitLoads(InstSeqNum &youngest_inst);
150
151 /** Commits stores older than a specific sequence number. */
152 void commitStores(InstSeqNum &youngest_inst);

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228 /** Handles doing the retry. */
229 void recvRetry();
230
231 private:
232 /** Reset the LSQ state */
233 void resetState();
234
235 /** Writes back the instruction, sending it to IEW. */
236 void writeback(DynInstPtr &inst, PacketPtr pkt);
236 void writeback(const DynInstPtr &inst, PacketPtr pkt);
237
238 /** Writes back a store that couldn't be completed the previous cycle. */
239 void writebackPendingStore();
240
241 /** Handles completing the send of a store to memory. */
242 void storePostSend(PacketPtr pkt);
243
244 /** Completes the store at the specified index. */

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308 /** Completes a packet and returns whether the access is finished. */
309 inline bool complete() { return --outstanding == 0; }
310 };
311
312 /** Writeback event, specifically for when stores forward data to loads. */
313 class WritebackEvent : public Event {
314 public:
315 /** Constructs a writeback event. */
237
238 /** Writes back a store that couldn't be completed the previous cycle. */
239 void writebackPendingStore();
240
241 /** Handles completing the send of a store to memory. */
242 void storePostSend(PacketPtr pkt);
243
244 /** Completes the store at the specified index. */

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308 /** Completes a packet and returns whether the access is finished. */
309 inline bool complete() { return --outstanding == 0; }
310 };
311
312 /** Writeback event, specifically for when stores forward data to loads. */
313 class WritebackEvent : public Event {
314 public:
315 /** Constructs a writeback event. */
316 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr);
316 WritebackEvent(const DynInstPtr &_inst, PacketPtr pkt,
317 LSQUnit *lsq_ptr);
317
318 /** Processes the writeback event. */
319 void process();
320
321 /** Returns the description of this event. */
322 const char *description() const;
323
324 private:

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343 }
344
345 ~SQEntry()
346 {
347 inst = NULL;
348 }
349
350 /** Constructs a store queue entry for a given instruction. */
318
319 /** Processes the writeback event. */
320 void process();
321
322 /** Returns the description of this event. */
323 const char *description() const;
324
325 private:

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344 }
345
346 ~SQEntry()
347 {
348 inst = NULL;
349 }
350
351 /** Constructs a store queue entry for a given instruction. */
351 SQEntry(DynInstPtr &_inst)
352 SQEntry(const DynInstPtr &_inst)
352 : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0),
353 isSplit(0), canWB(0), committed(0), completed(0), isAllZeros(0)
354 {
355 std::memset(data, 0, sizeof(data));
356 }
357 /** The store data. */
358 char data[16];
359 /** The store instruction. */

--- 534 unchanged lines hidden --- 		353 : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0),
354 isSplit(0), canWB(0), committed(0), completed(0), isAllZeros(0)
355 {
356 std::memset(data, 0, sizeof(data));
357 }
358 /** The store data. */
359 char data[16];
360 /** The store instruction. */

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