lsq_unit.hh (12171:b11b56bba18f) lsq_unit.hh (12355:568ec3a0c614)
1/*
1/*
2 * Copyright (c) 2012-2014 ARM Limited
2 * Copyright (c) 2012-2014,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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645 // Move the index to one younger
646 if (--store_idx < 0)
647 store_idx += SQEntries;
648
649 assert(storeQueue[store_idx].inst);
650
651 store_size = storeQueue[store_idx].size;
652
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 634 unchanged lines hidden (view full) ---

645 // Move the index to one younger
646 if (--store_idx < 0)
647 store_idx += SQEntries;
648
649 assert(storeQueue[store_idx].inst);
650
651 store_size = storeQueue[store_idx].size;
652
653 if (store_size == 0)
653 if (!store_size || storeQueue[store_idx].inst->strictlyOrdered() ||
654 (storeQueue[store_idx].req &&
655 storeQueue[store_idx].req->isCacheMaintenance())) {
656 // Cache maintenance instructions go down via the store
657 // path but they carry no data and they shouldn't be
658 // considered for forwarding
654 continue;
659 continue;
655 else if (storeQueue[store_idx].inst->strictlyOrdered())
656 continue;
660 }
657
658 assert(storeQueue[store_idx].inst->effAddrValid());
659
660 // Check if the store data is within the lower and upper bounds of
661 // addresses that the request needs.
662 bool store_has_lower_limit =
663 req->getVaddr() >= storeQueue[store_idx].inst->effAddr;
664 bool store_has_upper_limit =

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889 store_idx, req->getPaddr(), storeHead,
890 storeQueue[store_idx].inst->seqNum);
891
892 storeQueue[store_idx].req = req;
893 storeQueue[store_idx].sreqLow = sreqLow;
894 storeQueue[store_idx].sreqHigh = sreqHigh;
895 unsigned size = req->getSize();
896 storeQueue[store_idx].size = size;
661
662 assert(storeQueue[store_idx].inst->effAddrValid());
663
664 // Check if the store data is within the lower and upper bounds of
665 // addresses that the request needs.
666 bool store_has_lower_limit =
667 req->getVaddr() >= storeQueue[store_idx].inst->effAddr;
668 bool store_has_upper_limit =

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893 store_idx, req->getPaddr(), storeHead,
894 storeQueue[store_idx].inst->seqNum);
895
896 storeQueue[store_idx].req = req;
897 storeQueue[store_idx].sreqLow = sreqLow;
898 storeQueue[store_idx].sreqHigh = sreqHigh;
899 unsigned size = req->getSize();
900 storeQueue[store_idx].size = size;
897 storeQueue[store_idx].isAllZeros = req->getFlags() & Request::CACHE_BLOCK_ZERO;
898 assert(size <= sizeof(storeQueue[store_idx].data) ||
899 (req->getFlags() & Request::CACHE_BLOCK_ZERO));
901 bool store_no_data = req->getFlags() & Request::STORE_NO_DATA;
902 storeQueue[store_idx].isAllZeros = store_no_data;
903 assert(size <= sizeof(storeQueue[store_idx].data) || store_no_data);
900
901 // Split stores can only occur in ISAs with unaligned memory accesses. If
902 // a store request has been split, sreqLow and sreqHigh will be non-null.
903 if (TheISA::HasUnalignedMemAcc && sreqLow) {
904 storeQueue[store_idx].isSplit = true;
905 }
906
904
905 // Split stores can only occur in ISAs with unaligned memory accesses. If
906 // a store request has been split, sreqLow and sreqHigh will be non-null.
907 if (TheISA::HasUnalignedMemAcc && sreqLow) {
908 storeQueue[store_idx].isSplit = true;
909 }
910
907 if (!(req->getFlags() & Request::CACHE_BLOCK_ZERO))
911 if (!(req->getFlags() & Request::CACHE_BLOCK_ZERO) && \
912 !req->isCacheMaintenance())
908 memcpy(storeQueue[store_idx].data, data, size);
909
910 // This function only writes the data to the store queue, so no fault
911 // can happen here.
912 return NoFault;
913}
914
915#endif // __CPU_O3_LSQ_UNIT_HH__
913 memcpy(storeQueue[store_idx].data, data, size);
914
915 // This function only writes the data to the store queue, so no fault
916 // can happen here.
917 return NoFault;
918}
919
920#endif // __CPU_O3_LSQ_UNIT_HH__