lsq_unit.hh (11780:9af039ea0c1e) lsq_unit.hh (12022:256a709054f3)
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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666 (storeQueue[store_idx].inst->effAddr + store_size);
667 bool lower_load_has_store_part =
668 req->getVaddr() < (storeQueue[store_idx].inst->effAddr +
669 store_size);
670 bool upper_load_has_store_part =
671 (req->getVaddr() + req->getSize()) >
672 storeQueue[store_idx].inst->effAddr;
673
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 657 unchanged lines hidden (view full) ---

666 (storeQueue[store_idx].inst->effAddr + store_size);
667 bool lower_load_has_store_part =
668 req->getVaddr() < (storeQueue[store_idx].inst->effAddr +
669 store_size);
670 bool upper_load_has_store_part =
671 (req->getVaddr() + req->getSize()) >
672 storeQueue[store_idx].inst->effAddr;
673
674 // If the store's data has all of the data needed, we can forward.
675 if ((store_has_lower_limit && store_has_upper_limit)) {
674 // If the store's data has all of the data needed and the load isn't
675 // LLSC, we can forward.
676 if (store_has_lower_limit && store_has_upper_limit && !req->isLLSC()) {
676 // Get shift amount for offset into the store's data.
677 int shift_amt = req->getVaddr() - storeQueue[store_idx].inst->effAddr;
678
679 // Allocate memory if this is the first time a load is issued.
680 if (!load_inst->memData) {
681 load_inst->memData = new uint8_t[req->getSize()];
682 }
683 if (storeQueue[store_idx].isAllZeros)

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702 // Don't need to do anything special for split loads.
703 if (TheISA::HasUnalignedMemAcc && sreqLow) {
704 delete sreqLow;
705 delete sreqHigh;
706 }
707
708 ++lsqForwLoads;
709 return NoFault;
677 // Get shift amount for offset into the store's data.
678 int shift_amt = req->getVaddr() - storeQueue[store_idx].inst->effAddr;
679
680 // Allocate memory if this is the first time a load is issued.
681 if (!load_inst->memData) {
682 load_inst->memData = new uint8_t[req->getSize()];
683 }
684 if (storeQueue[store_idx].isAllZeros)

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703 // Don't need to do anything special for split loads.
704 if (TheISA::HasUnalignedMemAcc && sreqLow) {
705 delete sreqLow;
706 delete sreqHigh;
707 }
708
709 ++lsqForwLoads;
710 return NoFault;
710 } else if ((store_has_lower_limit && lower_load_has_store_part) ||
711 (store_has_upper_limit && upper_load_has_store_part) ||
712 (lower_load_has_store_part && upper_load_has_store_part)) {
711 } else if (
712 (!req->isLLSC() &&
713 ((store_has_lower_limit && lower_load_has_store_part) ||
714 (store_has_upper_limit && upper_load_has_store_part) ||
715 (lower_load_has_store_part && upper_load_has_store_part))) ||
716 (req->isLLSC() &&
717 ((store_has_lower_limit || upper_load_has_store_part) &&
718 (store_has_upper_limit || lower_load_has_store_part)))) {
713 // This is the partial store-load forwarding case where a store
719 // This is the partial store-load forwarding case where a store
714 // has only part of the load's data.
720 // has only part of the load's data and the load isn't LLSC or
721 // the load is LLSC and the store has all or part of the load's
722 // data
715
716 // If it's already been written back, then don't worry about
717 // stalling on it.
718 if (storeQueue[store_idx].completed) {
719 panic("Should not check one of these");
720 continue;
721 }
722

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724 // If it's already been written back, then don't worry about
725 // stalling on it.
726 if (storeQueue[store_idx].completed) {
727 panic("Should not check one of these");
728 continue;
729 }
730

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