lsq_unit.hh (11302:bce9037689b0) lsq_unit.hh (11780:9af039ea0c1e)
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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108 /** Takes over from another CPU's thread. */
109 void takeOverFrom();
110
111 /** Ticks the LSQ unit, which in this case only resets the number of
112 * used cache ports.
113 * @todo: Move the number of used ports up to the LSQ level so it can
114 * be shared by all LSQ units.
115 */
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 99 unchanged lines hidden (view full) ---

108 /** Takes over from another CPU's thread. */
109 void takeOverFrom();
110
111 /** Ticks the LSQ unit, which in this case only resets the number of
112 * used cache ports.
113 * @todo: Move the number of used ports up to the LSQ level so it can
114 * be shared by all LSQ units.
115 */
116 void tick() { usedPorts = 0; }
116 void tick() { usedStorePorts = 0; }
117
118 /** Inserts an instruction. */
119 void insert(DynInstPtr &inst);
120 /** Inserts a load instruction. */
121 void insertLoad(DynInstPtr &load_inst);
122 /** Inserts a store instruction. */
123 void insertStore(DynInstPtr &store_inst);
124

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424 /** The index of the first instruction that may be ready to be
425 * written back, and has not yet been written back.
426 */
427 int storeWBIdx;
428 /** The index of the tail instruction in the SQ. */
429 int storeTail;
430
431 /// @todo Consider moving to a more advanced model with write vs read ports
117
118 /** Inserts an instruction. */
119 void insert(DynInstPtr &inst);
120 /** Inserts a load instruction. */
121 void insertLoad(DynInstPtr &load_inst);
122 /** Inserts a store instruction. */
123 void insertStore(DynInstPtr &store_inst);
124

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424 /** The index of the first instruction that may be ready to be
425 * written back, and has not yet been written back.
426 */
427 int storeWBIdx;
428 /** The index of the tail instruction in the SQ. */
429 int storeTail;
430
431 /// @todo Consider moving to a more advanced model with write vs read ports
432 /** The number of cache ports available each cycle. */
433 int cachePorts;
432 /** The number of cache ports available each cycle (stores only). */
433 int cacheStorePorts;
434
434
435 /** The number of used cache ports in this cycle. */
436 int usedPorts;
435 /** The number of used cache ports in this cycle by stores. */
436 int usedStorePorts;
437
438 //list<InstSeqNum> mshrSeqNums;
439
440 /** Address Mask for a cache block (e.g. ~(cache_block_size-1)) */
441 Addr cacheBlockMask;
442
443 /** Wire to read information from the issue stage time queue. */
444 typename TimeBuffer<IssueStruct>::wire fromIssue;

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760 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %s\n",
761 load_inst->seqNum, load_inst->pcState());
762
763 // Allocate memory if this is the first time a load is issued.
764 if (!load_inst->memData) {
765 load_inst->memData = new uint8_t[req->getSize()];
766 }
767
437
438 //list<InstSeqNum> mshrSeqNums;
439
440 /** Address Mask for a cache block (e.g. ~(cache_block_size-1)) */
441 Addr cacheBlockMask;
442
443 /** Wire to read information from the issue stage time queue. */
444 typename TimeBuffer<IssueStruct>::wire fromIssue;

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760 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %s\n",
761 load_inst->seqNum, load_inst->pcState());
762
763 // Allocate memory if this is the first time a load is issued.
764 if (!load_inst->memData) {
765 load_inst->memData = new uint8_t[req->getSize()];
766 }
767
768 ++usedPorts;
769
770 // if we the cache is not blocked, do cache access
771 bool completedFirst = false;
772 PacketPtr data_pkt = Packet::createRead(req);
773 PacketPtr fst_data_pkt = NULL;
774 PacketPtr snd_data_pkt = NULL;
775
776 data_pkt->dataStatic(load_inst->memData);
777

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795 fst_data_pkt->senderState = state;
796 snd_data_pkt->senderState = state;
797
798 state->isSplit = true;
799 state->outstanding = 2;
800 state->mainPkt = data_pkt;
801 }
802
768 // if we the cache is not blocked, do cache access
769 bool completedFirst = false;
770 PacketPtr data_pkt = Packet::createRead(req);
771 PacketPtr fst_data_pkt = NULL;
772 PacketPtr snd_data_pkt = NULL;
773
774 data_pkt->dataStatic(load_inst->memData);
775

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793 fst_data_pkt->senderState = state;
794 snd_data_pkt->senderState = state;
795
796 state->isSplit = true;
797 state->outstanding = 2;
798 state->mainPkt = data_pkt;
799 }
800
801 // For now, load throughput is constrained by the number of
802 // load FUs only, and loads do not consume a cache port (only
803 // stores do).
804 // @todo We should account for cache port contention
805 // and arbitrate between loads and stores.
803 bool successful_load = true;
804 if (!dcachePort->sendTimingReq(fst_data_pkt)) {
805 successful_load = false;
806 } else if (TheISA::HasUnalignedMemAcc && sreqLow) {
807 completedFirst = true;
808
809 // The first packet was sent without problems, so send this one
810 // too. If there is a problem with this packet then the whole
811 // load will be squashed, so indicate this to the state object.
812 // The first packet will return in completeDataAccess and be
813 // handled there.
806 bool successful_load = true;
807 if (!dcachePort->sendTimingReq(fst_data_pkt)) {
808 successful_load = false;
809 } else if (TheISA::HasUnalignedMemAcc && sreqLow) {
810 completedFirst = true;
811
812 // The first packet was sent without problems, so send this one
813 // too. If there is a problem with this packet then the whole
814 // load will be squashed, so indicate this to the state object.
815 // The first packet will return in completeDataAccess and be
816 // handled there.
814 ++usedPorts;
817 // @todo We should also account for cache port contention
818 // here.
815 if (!dcachePort->sendTimingReq(snd_data_pkt)) {
816 // The main packet will be deleted in completeDataAccess.
817 state->complete();
818 // Signify to 1st half that the 2nd half was blocked via state
819 state->cacheBlocked = true;
820 successful_load = false;
821 }
822 }

--- 81 unchanged lines hidden --- 		819 if (!dcachePort->sendTimingReq(snd_data_pkt)) {
820 // The main packet will be deleted in completeDataAccess.
821 state->complete();
822 // Signify to 1st half that the 2nd half was blocked via state
823 state->cacheBlocked = true;
824 successful_load = false;
825 }
826 }

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