lsq_unit.hh (10333:6be8945d226b) lsq_unit.hh (10342:711eb0e64249)
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 762 unchanged lines hidden (view full) ---

771 if (!load_inst->memData) {
772 load_inst->memData = new uint8_t[req->getSize()];
773 }
774
775 ++usedPorts;
776
777 // if we the cache is not blocked, do cache access
778 bool completedFirst = false;
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 762 unchanged lines hidden (view full) ---

771 if (!load_inst->memData) {
772 load_inst->memData = new uint8_t[req->getSize()];
773 }
774
775 ++usedPorts;
776
777 // if we the cache is not blocked, do cache access
778 bool completedFirst = false;
779 MemCmd command = req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq;
780 PacketPtr data_pkt = new Packet(req, command);
779 PacketPtr data_pkt = Packet::createRead(req);
781 PacketPtr fst_data_pkt = NULL;
782 PacketPtr snd_data_pkt = NULL;
783
784 data_pkt->dataStatic(load_inst->memData);
785
786 LSQSenderState *state = new LSQSenderState;
787 state->isLoad = true;
788 state->idx = load_idx;
789 state->inst = load_inst;
790 data_pkt->senderState = state;
791
792 if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
793 // Point the first packet at the main data packet.
794 fst_data_pkt = data_pkt;
795 } else {
796 // Create the split packets.
780 PacketPtr fst_data_pkt = NULL;
781 PacketPtr snd_data_pkt = NULL;
782
783 data_pkt->dataStatic(load_inst->memData);
784
785 LSQSenderState *state = new LSQSenderState;
786 state->isLoad = true;
787 state->idx = load_idx;
788 state->inst = load_inst;
789 data_pkt->senderState = state;
790
791 if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
792 // Point the first packet at the main data packet.
793 fst_data_pkt = data_pkt;
794 } else {
795 // Create the split packets.
797 fst_data_pkt = new Packet(sreqLow, command);
798 snd_data_pkt = new Packet(sreqHigh, command);
796 fst_data_pkt = Packet::createRead(sreqLow);
797 snd_data_pkt = Packet::createRead(sreqHigh);
799
800 fst_data_pkt->dataStatic(load_inst->memData);
801 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
802
803 fst_data_pkt->senderState = state;
804 snd_data_pkt->senderState = state;
805
806 state->isSplit = true;

--- 105 unchanged lines hidden --- 		798
799 fst_data_pkt->dataStatic(load_inst->memData);
800 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
801
802 fst_data_pkt->senderState = state;
803 snd_data_pkt->senderState = state;
804
805 state->isSplit = true;

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