lsq_unit.hh (10239:592f0bb6bd6f) lsq_unit.hh (10327:5b6279635c49)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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757 stalled = true;
758 stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
759 stallingLoadIdx = load_idx;
760 }
761
762 // Tell IQ/mem dep unit that this instruction will need to be
763 // rescheduled eventually
764 iewStage->rescheduleMemInst(load_inst);
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 748 unchanged lines hidden (view full) ---

757 stalled = true;
758 stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
759 stallingLoadIdx = load_idx;
760 }
761
762 // Tell IQ/mem dep unit that this instruction will need to be
763 // rescheduled eventually
764 iewStage->rescheduleMemInst(load_inst);
765 iewStage->decrWb(load_inst->seqNum);
766 load_inst->clearIssued();
767 ++lsqRescheduledLoads;
768
769 // Do not generate a writeback event as this instruction is not
770 // complete.
771 DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
772 "Store idx %i to load addr %#x\n",
773 store_idx, req->getVaddr());

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884 delete req;
885 if (TheISA::HasUnalignedMemAcc && sreqLow && !completedFirst) {
886 delete sreqLow;
887 delete sreqHigh;
888 }
889
890 ++lsqCacheBlocked;
891
765 load_inst->clearIssued();
766 ++lsqRescheduledLoads;
767
768 // Do not generate a writeback event as this instruction is not
769 // complete.
770 DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
771 "Store idx %i to load addr %#x\n",
772 store_idx, req->getVaddr());

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883 delete req;
884 if (TheISA::HasUnalignedMemAcc && sreqLow && !completedFirst) {
885 delete sreqLow;
886 delete sreqHigh;
887 }
888
889 ++lsqCacheBlocked;
890
892 // If the first part of a split access succeeds, then let the LSQ
893 // handle the decrWb when completeDataAccess is called upon return
894 // of the requested first part of data
895 if (!completedFirst)
896 iewStage->decrWb(load_inst->seqNum);
897
898 // There's an older load that's already going to squash.
899 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
900 return NoFault;
901
902 // Record that the load was blocked due to memory. This
903 // load will squash all instructions after it, be
904 // refetched, and re-executed.
905 isLoadBlocked = true;

--- 45 unchanged lines hidden --- 		891 // There's an older load that's already going to squash.
892 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
893 return NoFault;
894
895 // Record that the load was blocked due to memory. This
896 // load will squash all instructions after it, be
897 // refetched, and re-executed.
898 isLoadBlocked = true;

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