lsq_unit.hh (10031:79d034cd6ba3) lsq_unit.hh (10175:e639ff917d2e)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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706 load_inst->memData = new uint8_t[req->getSize()];
707 if (storeQueue[store_idx].isAllZeros)
708 memset(load_inst->memData, 0, req->getSize());
709 else
710 memcpy(load_inst->memData,
711 storeQueue[store_idx].data + shift_amt, req->getSize());
712
713 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 697 unchanged lines hidden (view full) ---

706 load_inst->memData = new uint8_t[req->getSize()];
707 if (storeQueue[store_idx].isAllZeros)
708 memset(load_inst->memData, 0, req->getSize());
709 else
710 memcpy(load_inst->memData,
711 storeQueue[store_idx].data + shift_amt, req->getSize());
712
713 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
714 "addr %#x, data %#x\n",
715 store_idx, req->getVaddr(), data);
714 "addr %#x\n", store_idx, req->getVaddr());
716
717 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
718 data_pkt->dataStatic(load_inst->memData);
719
720 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
721
722 // We'll say this has a 1 cycle load-store forwarding latency
723 // for now.

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911
912template <class Impl>
913Fault
914LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh,
915 uint8_t *data, int store_idx)
916{
917 assert(storeQueue[store_idx].inst);
918
715
716 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
717 data_pkt->dataStatic(load_inst->memData);
718
719 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
720
721 // We'll say this has a 1 cycle load-store forwarding latency
722 // for now.

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910
911template <class Impl>
912Fault
913LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh,
914 uint8_t *data, int store_idx)
915{
916 assert(storeQueue[store_idx].inst);
917
919 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x"
918 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x"
920 " | storeHead:%i [sn:%i]\n",
919 " | storeHead:%i [sn:%i]\n",
921 store_idx, req->getPaddr(), data, storeHead,
920 store_idx, req->getPaddr(), storeHead,
922 storeQueue[store_idx].inst->seqNum);
923
924 storeQueue[store_idx].req = req;
925 storeQueue[store_idx].sreqLow = sreqLow;
926 storeQueue[store_idx].sreqHigh = sreqHigh;
927 unsigned size = req->getSize();
928 storeQueue[store_idx].size = size;
929 storeQueue[store_idx].isAllZeros = req->getFlags() & Request::CACHE_BLOCK_ZERO;

--- 18 unchanged lines hidden --- 		921 storeQueue[store_idx].inst->seqNum);
922
923 storeQueue[store_idx].req = req;
924 storeQueue[store_idx].sreqLow = sreqLow;
925 storeQueue[store_idx].sreqHigh = sreqHigh;
926 unsigned size = req->getSize();
927 storeQueue[store_idx].size = size;
928 storeQueue[store_idx].isAllZeros = req->getFlags() & Request::CACHE_BLOCK_ZERO;

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