1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 787 unchanged lines hidden (view full) --- 796 fst_data_pkt->senderState = state; 797 snd_data_pkt->senderState = state; 798 799 state->isSplit = true; 800 state->outstanding = 2; 801 state->mainPkt = data_pkt; 802 } 803 |
804 if (!dcachePort->sendTimingReq(fst_data_pkt)) { |
805 // Delete state and data packet because a load retry 806 // initiates a pipeline restart; it does not retry. 807 delete state; 808 delete data_pkt->req; 809 delete data_pkt; 810 if (TheISA::HasUnalignedMemAcc && sreqLow) { 811 delete fst_data_pkt->req; 812 delete fst_data_pkt; --- 12 unchanged lines hidden (view full) --- 825 completedFirst = true; 826 827 // The first packet was sent without problems, so send this one 828 // too. If there is a problem with this packet then the whole 829 // load will be squashed, so indicate this to the state object. 830 // The first packet will return in completeDataAccess and be 831 // handled there. 832 ++usedPorts; |
833 if (!dcachePort->sendTimingReq(snd_data_pkt)) { |
834 835 // The main packet will be deleted in completeDataAccess. 836 delete snd_data_pkt->req; 837 delete snd_data_pkt; 838 839 state->complete(); 840 841 req = NULL; --- 75 unchanged lines hidden --- |