1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 790 unchanged lines hidden (view full) --- 799 delete req; 800 if (TheISA::HasUnalignedMemAcc && sreqLow && !completedFirst) { 801 delete sreqLow; 802 delete sreqHigh; 803 } 804 805 ++lsqCacheBlocked; 806 |
807 // If the first part of a split access succeeds, then let the LSQ 808 // handle the decrWb when completeDataAccess is called upon return 809 // of the requested first part of data 810 if (!completedFirst) 811 iewStage->decrWb(load_inst->seqNum); 812 |
813 // There's an older load that's already going to squash. 814 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum) 815 return NoFault; 816 817 // Record that the load was blocked due to memory. This 818 // load will squash all instructions after it, be 819 // refetched, and re-executed. 820 isLoadBlocked = true; --- 42 unchanged lines hidden --- |