1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 495 unchanged lines hidden (view full) --- 504 int store_idx = load_inst->sqIdx; 505 506 int store_size = 0; 507 508 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, " 509 "storeHead: %i addr: %#x\n", 510 load_idx, store_idx, storeHead, req->getPaddr()); 511 |
512 if (req->isLocked()) { 513 // Disable recording the result temporarily. Writing to misc 514 // regs normally updates the result, but this is not the 515 // desired behavior when handling store conditionals. 516 load_inst->recordResult = false; 517 TheISA::handleLockedRead(load_inst.get(), req); 518 load_inst->recordResult = true; 519 } |
520 521 while (store_idx != -1) { 522 // End once we've reached the top of the LSQ 523 if (store_idx == storeWBIdx) { 524 break; 525 } 526 527 // Move the index to one younger --- 26 unchanged lines hidden (view full) --- 554 // Get shift amount for offset into the store's data. 555 int shift_amt = req->getVaddr() & (store_size - 1); 556 // @todo: Magic number, assumes byte addressing 557 shift_amt = shift_amt << 3; 558 559 // Cast this to type T? 560 data = storeQueue[store_idx].data >> shift_amt; 561 |
562 assert(!load_inst->memData); 563 load_inst->memData = new uint8_t[64]; 564 565 memcpy(load_inst->memData, &data, req->getSize()); 566 567 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to " 568 "addr %#x, data %#x\n", 569 store_idx, req->getVaddr(), data); --- 137 unchanged lines hidden --- |