1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 547 unchanged lines hidden (view full) --- 556 // Get shift amount for offset into the store's data. 557 int shift_amt = req->getVaddr() & (store_size - 1); 558 // @todo: Magic number, assumes byte addressing 559 shift_amt = shift_amt << 3; 560 561 // Cast this to type T? 562 data = storeQueue[store_idx].data >> shift_amt; 563 |
564 // When the data comes from the store queue entry, it's in host 565 // order. When it gets sent to the load, it needs to be in guest 566 // order so when the load converts it again, it ends up back 567 // in host order like the inst expects. 568 data = TheISA::htog(data); 569 |
570 assert(!load_inst->memData); 571 load_inst->memData = new uint8_t[64]; 572 573 memcpy(load_inst->memData, &data, req->getSize()); 574 575 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to " 576 "addr %#x, data %#x\n", 577 store_idx, req->getVaddr(), data); --- 137 unchanged lines hidden --- |