1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 393 unchanged lines hidden (view full) --- 402 InstSeqNum blockedLoadSeqNum; 403 404 /** The oldest load that caused a memory ordering violation. */ 405 DynInstPtr memDepViolator; 406 407 // Will also need how many read/write ports the Dcache has. Or keep track 408 // of that in stage that is one level up, and only call executeLoad/Store 409 // the appropriate number of times. |
410 /** Total number of loads forwaded from LSQ stores. */ 411 Stats::Scalar<> lsqForwLoads; 412 |
413 /** Total number of squashed stores. */ 414 Stats::Scalar<> lsqSquashedStores; 415 416 /** Total number of software prefetches ignored due to invalid addresses. */ 417 Stats::Scalar<> invAddrSwpfs; 418 419 /** Ready loads blocked due to partial store-forwarding. */ 420 Stats::Scalar<> lsqBlockedLoads; --- 268 unchanged lines hidden --- |