1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 28 unchanged lines hidden (view full) --- 37#include <queue> 38 39#include "arch/faults.hh" 40#include "config/full_system.hh" 41#include "base/hashmap.hh" 42#include "cpu/inst_seq.hh" 43#include "mem/packet.hh" 44#include "mem/port.hh" |
45 46/** 47 * Class that implements the actual LQ and SQ for each specific 48 * thread. Both are circular queues; load entries are freed upon 49 * committing, while store entries are freed once they writeback. The 50 * LSQUnit tracks if there are memory ordering violations, and also 51 * detects partial load to store forwarding cases (a store only has 52 * part of a load's data) that requires the load to wait until the --- 26 unchanged lines hidden (view full) --- 79 80 /** Sets the CPU pointer. */ 81 void setCPU(FullCPU *cpu_ptr); 82 83 /** Sets the IEW stage pointer. */ 84 void setIEW(IEW *iew_ptr) 85 { iewStage = iew_ptr; } 86 |
87 /** Switches out LSQ unit. */ 88 void switchOut(); 89 90 /** Takes over from another CPU's thread. */ 91 void takeOverFrom(); 92 93 /** Returns if the LSQ is switched out. */ 94 bool isSwitchedOut() { return switchedOut; } --- 105 unchanged lines hidden (view full) --- 200 int numStoresToWB() { return storesToWB; } 201 202 /** Returns if the LSQ unit will writeback on this cycle. */ 203 bool willWB() { return storeQueue[storeWBIdx].canWB && 204 !storeQueue[storeWBIdx].completed && 205 !isStoreBlocked; } 206 207 private: |
208 /** Writes back the instruction, sending it to IEW. */ |
209 void writeback(DynInstPtr &inst, PacketPtr pkt); 210 |
211 /** Handles completing the send of a store to memory. */ |
212 void storePostSend(Packet *pkt); 213 214 /** Completes the store at the specified index. */ 215 void completeStore(int store_idx); 216 217 /** Handles doing the retry. */ 218 void recvRetry(); 219 --- 12 unchanged lines hidden (view full) --- 232 233 private: 234 /** Pointer to the CPU. */ 235 FullCPU *cpu; 236 237 /** Pointer to the IEW stage. */ 238 IEW *iewStage; 239 |
240 /** Pointer to memory object. */ |
241 MemObject *mem; 242 |
243 /** DcachePort class for this LSQ Unit. Handles doing the 244 * communication with the cache/memory. 245 * @todo: Needs to be moved to the LSQ level and have some sort 246 * of arbitration. 247 */ |
248 class DcachePort : public Port 249 { 250 protected: |
251 /** Pointer to CPU. */ |
252 FullCPU *cpu; |
253 /** Pointer to LSQ. */ |
254 LSQUnit *lsq; 255 256 public: |
257 /** Default constructor. */ |
258 DcachePort(FullCPU *_cpu, LSQUnit *_lsq) 259 : Port(_lsq->name() + "-dport"), cpu(_cpu), lsq(_lsq) 260 { } 261 262 protected: |
263 /** Atomic version of receive. Panics. */ |
264 virtual Tick recvAtomic(PacketPtr pkt); 265 |
266 /** Functional version of receive. Panics. */ |
267 virtual void recvFunctional(PacketPtr pkt); 268 |
269 /** Receives status change. Other than range changing, panics. */ |
270 virtual void recvStatusChange(Status status); 271 |
272 /** Returns the address ranges of this device. */ |
273 virtual void getDeviceAddressRanges(AddrRangeList &resp, 274 AddrRangeList &snoop) 275 { resp.clear(); snoop.clear(); } 276 |
277 /** Timing version of receive. Handles writing back and 278 * completing the load or store that has returned from 279 * memory. */ |
280 virtual bool recvTiming(PacketPtr pkt); 281 |
282 /** Handles doing a retry of the previous send. */ |
283 virtual void recvRetry(); 284 }; 285 286 /** Pointer to the D-cache. */ 287 DcachePort *dcachePort; 288 |
289 /** Derived class to hold any sender state the LSQ needs. */ |
290 class LSQSenderState : public Packet::SenderState 291 { 292 public: |
293 /** Default constructor. */ |
294 LSQSenderState() 295 : noWB(false) 296 { } 297 |
298 /** Instruction who initiated the access to memory. */ |
299 DynInstPtr inst; |
300 /** Whether or not it is a load. */ |
301 bool isLoad; |
302 /** The LQ/SQ index of the instruction. */ |
303 int idx; |
304 /** Whether or not the instruction will need to writeback. */ |
305 bool noWB; 306 }; 307 |
308 /** Writeback event, specifically for when stores forward data to loads. */ |
309 class WritebackEvent : public Event { 310 public: 311 /** Constructs a writeback event. */ 312 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr); 313 314 /** Processes the writeback event. */ 315 void process(); 316 317 /** Returns the description of this event. */ 318 const char *description(); 319 320 private: |
321 /** Instruction whose results are being written back. */ |
322 DynInstPtr inst; 323 |
324 /** The packet that would have been sent to memory. */ |
325 PacketPtr pkt; 326 327 /** The pointer to the LSQ unit that issued the store. */ 328 LSQUnit<Impl> *lsqPtr; 329 }; 330 331 public: 332 struct SQEntry { --- 84 unchanged lines hidden (view full) --- 417 bool stalled; 418 /** The store that causes the stall due to partial store to load 419 * forwarding. 420 */ 421 InstSeqNum stallingStoreIsn; 422 /** The index of the above store. */ 423 int stallingLoadIdx; 424 |
425 /** The packet that needs to be retried. */ 426 PacketPtr retryPkt; |
427 |
428 /** Whehter or not a store is blocked due to the memory system. */ |
429 bool isStoreBlocked; 430 431 /** Whether or not a load is blocked due to the memory system. */ 432 bool isLoadBlocked; 433 434 /** Has the blocked load been handled. */ 435 bool loadBlockedHandled; 436 --- 275 unchanged lines hidden --- |