1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 199 unchanged lines hidden (view full) --- 208 /** Returns if the LSQ unit will writeback on this cycle. */ 209 bool willWB() { return storeQueue[storeWBIdx].canWB && 210 !storeQueue[storeWBIdx].completed && 211 !isStoreBlocked; } 212 213 private: 214 void writeback(DynInstPtr &inst, PacketPtr pkt); 215 |
216 void storePostSend(Packet *pkt); 217 |
218 /** Completes the store at the specified index. */ 219 void completeStore(int store_idx); 220 |
221 /** Handles doing the retry. */ 222 void recvRetry(); 223 |
224 /** Increments the given store index (circular queue). */ 225 inline void incrStIdx(int &store_idx); 226 /** Decrements the given store index (circular queue). */ 227 inline void decrStIdx(int &store_idx); 228 /** Increments the given load index (circular queue). */ 229 inline void incrLdIdx(int &load_idx); 230 /** Decrements the given load index (circular queue). */ 231 inline void decrLdIdx(int &load_idx); --- 167 unchanged lines hidden (view full) --- 399 bool stalled; 400 /** The store that causes the stall due to partial store to load 401 * forwarding. 402 */ 403 InstSeqNum stallingStoreIsn; 404 /** The index of the above store. */ 405 int stallingLoadIdx; 406 |
407 PacketPtr sendingPkt; 408 |
409 bool isStoreBlocked; 410 411 /** Whether or not a load is blocked due to the memory system. */ 412 bool isLoadBlocked; 413 414 /** Has the blocked load been handled. */ 415 bool loadBlockedHandled; 416 --- 89 unchanged lines hidden (view full) --- 506 int store_idx = load_inst->sqIdx; 507 508 int store_size = 0; 509 510 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, " 511 "storeHead: %i addr: %#x\n", 512 load_idx, store_idx, storeHead, req->getPaddr()); 513 |
514#if FULL_SYSTEM |
515 if (req->getFlags() & LOCKED) { 516 cpu->lockAddr = req->getPaddr(); 517 cpu->lockFlag = true; 518 } 519#endif 520 521 while (store_idx != -1) { 522 // End once we've reached the top of the LSQ --- 38 unchanged lines hidden (view full) --- 561 562 assert(!load_inst->memData); 563 load_inst->memData = new uint8_t[64]; 564 565 memcpy(load_inst->memData, &data, req->getSize()); 566 567 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to " 568 "addr %#x, data %#x\n", |
569 store_idx, req->getVaddr(), data); |
570 571 PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast); 572 data_pkt->dataStatic(load_inst->memData); 573 574 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this); 575 576 // We'll say this has a 1 cycle load-store forwarding latency 577 // for now. --- 114 unchanged lines hidden --- |