1/* 2 * Copyright (c) 2012-2014,2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 37 unchanged lines hidden (view full) --- 46#define __CPU_O3_LSQ_UNIT_HH__ 47 48#include <algorithm> 49#include <cstring> 50#include <map> 51#include <queue> 52 53#include "arch/generic/debugfaults.hh" |
54#include "arch/generic/vec_reg.hh" |
55#include "arch/isa_traits.hh" 56#include "arch/locked_mem.hh" 57#include "arch/mmapped_ipr.hh" 58#include "config/the_isa.hh" 59#include "cpu/inst_seq.hh" 60#include "cpu/timebuf.hh" 61#include "debug/LSQUnit.hh" 62#include "mem/packet.hh" --- 13 unchanged lines hidden (view full) --- 76 * until the dependence unit looks at it, and in the latter it stalls 77 * the LSQ until the store writes back. At that point the load is 78 * replayed. 79 */ 80template <class Impl> 81class LSQUnit 82{ 83 public: |
84 static constexpr auto MaxDataBytes = MaxVecRegLenInBytes; 85 |
86 typedef typename Impl::O3CPU O3CPU; 87 typedef typename Impl::DynInstPtr DynInstPtr; 88 typedef typename Impl::CPUPol::IEW IEW; 89 typedef typename Impl::CPUPol::LSQ LSQ; 90 typedef typename Impl::CPUPol::IssueStruct IssueStruct; 91 92 using LSQSenderState = typename LSQ::LSQSenderState; 93 using LSQRequest = typename Impl::CPUPol::LSQ::LSQRequest; 94 private: 95 class LSQEntry 96 { 97 private: 98 /** The instruction. */ 99 DynInstPtr inst; 100 /** The request. */ 101 LSQRequest* req; 102 /** The size of the operation. */ |
103 uint32_t _size; |
104 /** Valid entry. */ 105 bool _valid; 106 public: 107 /** Constructs an empty store queue entry. */ 108 LSQEntry() 109 : inst(nullptr), req(nullptr), _size(0), _valid(false) 110 { 111 } --- 28 unchanged lines hidden (view full) --- 140 _size = 0; 141 } 142 LSQRequest* request() { return req; } 143 void setRequest(LSQRequest* r) { req = r; } 144 bool hasRequest() { return req != nullptr; } 145 /** Member accessors. */ 146 /** @{ */ 147 bool valid() const { return _valid; } |
148 uint32_t& size() { return _size; } 149 const uint32_t& size() const { return _size; } |
150 const DynInstPtr& instruction() const { return inst; } 151 /** @} */ 152 }; 153 154 class SQEntry : public LSQEntry 155 { 156 private: 157 /** The store data. */ |
158 char _data[MaxDataBytes]; |
159 /** Whether or not the store can writeback. */ 160 bool _canWB; 161 /** Whether or not the store is committed. */ 162 bool _committed; 163 /** Whether or not the store is completed. */ 164 bool _completed; 165 /** Does this request write all zeros and thus doesn't 166 * have any data attached to it. Used for cache block zero --- 490 unchanged lines hidden (view full) --- 657 // desired behavior when handling store conditionals. 658 load_inst->recordResult(false); 659 TheISA::handleLockedRead(load_inst.get(), req->mainRequest()); 660 load_inst->recordResult(true); 661 } 662 663 if (req->mainRequest()->isMmappedIpr()) { 664 assert(!load_inst->memData); |
665 load_inst->memData = new uint8_t[MaxDataBytes]; |
666 667 ThreadContext *thread = cpu->tcBase(lsqID); 668 PacketPtr main_pkt = new Packet(req->mainRequest(), MemCmd::ReadReq); 669 670 Cycles delay = req->handleIprRead(thread, main_pkt); 671 672 WritebackEvent *wb = new WritebackEvent(load_inst, main_pkt, this); 673 cpu->schedule(wb, cpu->clockEdge(delay)); --- 208 unchanged lines hidden --- |