1/* 2 * Copyright (c) 2012-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 497 unchanged lines hidden (view full) --- 506 Stats::Scalar lsqRescheduledLoads; 507 508 /** Number of times the LSQ is blocked due to the cache. */ 509 Stats::Scalar lsqCacheBlocked; 510 511 public: 512 /** Executes the load at the given index. */ 513 Fault read(Request *req, Request *sreqLow, Request *sreqHigh, |
514 int load_idx); |
515 516 /** Executes the store at the given index. */ 517 Fault write(Request *req, Request *sreqLow, Request *sreqHigh, 518 uint8_t *data, int store_idx); 519 520 /** Returns the index of the head load instruction. */ 521 int getLoadHead() { return loadHead; } 522 /** Returns the sequence number of the head load instruction. */ --- 22 unchanged lines hidden (view full) --- 545 546 /** Returns whether or not the LSQ unit is stalled. */ 547 bool isStalled() { return stalled; } 548}; 549 550template <class Impl> 551Fault 552LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, |
553 int load_idx) |
554{ 555 DynInstPtr load_inst = loadQueue[load_idx]; 556 557 assert(load_inst); 558 559 assert(!load_inst->isExecuted()); 560 561 // Make sure this isn't a strictly ordered load --- 109 unchanged lines hidden (view full) --- 671 (req->getVaddr() + req->getSize()) > 672 storeQueue[store_idx].inst->effAddr; 673 674 // If the store's data has all of the data needed, we can forward. 675 if ((store_has_lower_limit && store_has_upper_limit)) { 676 // Get shift amount for offset into the store's data. 677 int shift_amt = req->getVaddr() - storeQueue[store_idx].inst->effAddr; 678 |
679 // Allocate memory if this is the first time a load is issued. 680 if (!load_inst->memData) { 681 load_inst->memData = new uint8_t[req->getSize()]; 682 } 683 if (storeQueue[store_idx].isAllZeros) 684 memset(load_inst->memData, 0, req->getSize()); 685 else 686 memcpy(load_inst->memData, --- 217 unchanged lines hidden --- |