2c2
< * Copyright (c) 2012 ARM Limited
---
> * Copyright (c) 2012-2013 ARM Limited
364c364
< isSplit(0), canWB(0), committed(0), completed(0)
---
> isSplit(0), canWB(0), committed(0), completed(0), isAllZeros(0)
386a387,391
> /** Does this request write all zeros and thus doesn't
> * have any data attached to it. Used for cache block zero
> * style instructs (ARM DC ZVA; ALPHA WH64)
> */
> bool isAllZeros;
694c699,702
< memcpy(data, storeQueue[store_idx].data + shift_amt,
---
> if (storeQueue[store_idx].isAllZeros)
> memset(data, 0, req->getSize());
> else
> memcpy(data, storeQueue[store_idx].data + shift_amt,
698,700c706,710
< load_inst->memData = new uint8_t[64];
<
< memcpy(load_inst->memData,
---
> load_inst->memData = new uint8_t[req->getSize()];
> if (storeQueue[store_idx].isAllZeros)
> memset(load_inst->memData, 0, req->getSize());
> else
> memcpy(load_inst->memData,
780c790
< load_inst->memData = new uint8_t[64];
---
> load_inst->memData = new uint8_t[req->getSize()];
919c929,931
< assert(size <= sizeof(storeQueue[store_idx].data));
---
> storeQueue[store_idx].isAllZeros = req->getFlags() & Request::CACHE_BLOCK_ZERO;
> assert(size <= sizeof(storeQueue[store_idx].data) ||
> (req->getFlags() & Request::CACHE_BLOCK_ZERO));
927c939,940
< memcpy(storeQueue[store_idx].data, data, size);
---
> if (!(req->getFlags() & Request::CACHE_BLOCK_ZERO))
> memcpy(storeQueue[store_idx].data, data, size);