292c292
< : inst(NULL), req(NULL), size(0), data(0),
---
> : inst(NULL), req(NULL), size(0),
294c294,296
< { }
---
> {
> bzero(data, sizeof(data));
> }
298c300
< : inst(_inst), req(NULL), size(0), data(0),
---
> : inst(_inst), req(NULL), size(0),
300c302,304
< { }
---
> {
> bzero(data, sizeof(data));
> }
309c313
< IntReg data;
---
> char data[sizeof(IntReg)];
557,558d560
< // @todo: Magic number, assumes byte addressing
< shift_amt = shift_amt << 3;
560,561c562
< // Cast this to type T?
< data = storeQueue[store_idx].data >> shift_amt;
---
> memcpy(&data, storeQueue[store_idx].data + shift_amt, sizeof(T));
563,568d563
< // When the data comes from the store queue entry, it's in host
< // order. When it gets sent to the load, it needs to be in guest
< // order so when the load converts it again, it ends up back
< // in host order like the inst expects.
< data = TheISA::htog(data);
<
572c567,568
< memcpy(load_inst->memData, &data, req->getSize());
---
> memcpy(load_inst->memData,
> storeQueue[store_idx].data + shift_amt, req->getSize());
719c715
< storeQueue[store_idx].data = data;
---
> assert(sizeof(T) <= sizeof(storeQueue[store_idx].data));
720a717,719
> T gData = htog(data);
> memcpy(storeQueue[store_idx].data, &gData, sizeof(T));
>