300c300
< : inst(NULL), req(NULL), size(0), data(0),
---
> : inst(NULL), req(NULL), size(0),
302c302,304
< { }
---
> {
> bzero(data, sizeof(data));
> }
306c308
< : inst(_inst), req(NULL), size(0), data(0),
---
> : inst(_inst), req(NULL), size(0),
308c310,312
< { }
---
> {
> bzero(data, sizeof(data));
> }
317c321
< IntReg data;
---
> char data[sizeof(IntReg)];
565,566d568
< // @todo: Magic number, assumes byte addressing
< shift_amt = shift_amt << 3;
568,569c570
< // Cast this to type T?
< data = storeQueue[store_idx].data >> shift_amt;
---
> memcpy(&data, storeQueue[store_idx].data + shift_amt, sizeof(T));
571,576d571
< // When the data comes from the store queue entry, it's in host
< // order. When it gets sent to the load, it needs to be in guest
< // order so when the load converts it again, it ends up back
< // in host order like the inst expects.
< data = TheISA::htog(data);
<
580c575,576
< memcpy(load_inst->memData, &data, req->getSize());
---
> memcpy(load_inst->memData,
> storeQueue[store_idx].data + shift_amt, req->getSize());
727c723
< storeQueue[store_idx].data = data;
---
> assert(sizeof(T) <= sizeof(storeQueue[store_idx].data));
728a725,727
> T gData = htog(data);
> memcpy(storeQueue[store_idx].data, &gData, sizeof(T));
>