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> typedef typename Impl::CPUPol::LSQ LSQ;
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< void init(Params *params, unsigned maxLQEntries,
---
> void init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
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< /** Returns the dcache port.
< * @todo: Remove this once the port moves up to the LSQ level.
< */
< Port *getDcachePort() { return dcachePort; }
<
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> /** Sets the pointer to the dcache port. */
> void setDcachePort(Port *dcache_port)
> { dcachePort = dcache_port; }
>
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> /** Handles doing the retry. */
> void recvRetry();
>
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< /** Handles doing the retry. */
< void recvRetry();
<
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< /** Pointer to memory object. */
< MemObject *mem;
---
> /** Pointer to the LSQ. */
> LSQ *lsq;
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< /** DcachePort class for this LSQ Unit. Handles doing the
< * communication with the cache/memory.
< * @todo: Needs to be moved to the LSQ level and have some sort
< * of arbitration.
< */
< class DcachePort : public Port
< {
< protected:
< /** Pointer to CPU. */
< O3CPU *cpu;
< /** Pointer to LSQ. */
< LSQUnit *lsq;
---
> /** Pointer to the dcache port. Used only for sending. */
> Port *dcachePort;
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< public:
< /** Default constructor. */
< DcachePort(O3CPU *_cpu, LSQUnit *_lsq)
< : Port(_lsq->name() + "-dport"), cpu(_cpu), lsq(_lsq)
< { }
<
< protected:
< /** Atomic version of receive. Panics. */
< virtual Tick recvAtomic(PacketPtr pkt);
<
< /** Functional version of receive. Panics. */
< virtual void recvFunctional(PacketPtr pkt);
<
< /** Receives status change. Other than range changing, panics. */
< virtual void recvStatusChange(Status status);
<
< /** Returns the address ranges of this device. */
< virtual void getDeviceAddressRanges(AddrRangeList &resp,
< AddrRangeList &snoop)
< { resp.clear(); snoop.clear(); }
<
< /** Timing version of receive. Handles writing back and
< * completing the load or store that has returned from
< * memory. */
< virtual bool recvTiming(PacketPtr pkt);
<
< /** Handles doing a retry of the previous send. */
< virtual void recvRetry();
< };
<
< /** Pointer to the D-cache. */
< DcachePort *dcachePort;
<
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< DPRINTF(LSQUnit, "Doing functional access for inst [sn:%lli] PC %#x\n",
---
> DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %#x\n",
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< DPRINTF(LSQUnit, "Doing timing access for inst PC %#x\n",
< load_inst->readPC());
<
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< // if we have a cache, do cache access too
< if (!dcachePort->sendTiming(data_pkt)) {
---
> // if we the cache is not blocked, do cache access
> if (!lsq->cacheBlocked()) {
> if (!dcachePort->sendTiming(data_pkt)) {
> // If the access didn't succeed, tell the LSQ by setting
> // the retry thread id.
> lsq->setRetryTid(lsqID);
> }
> }
>
> // If the cache was blocked, or has become blocked due to the access,
> // handle it.
> if (lsq->cacheBlocked()) {