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> /** Registers statistics. */
> void regStats();
>
130,132d132
< // @todo: Include stats in the LSQ unit.
< //void regStats();
<
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< /*
< // total number of loads forwaded from LSQ stores
< Stats::Vector<> lsq_forw_loads;
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< // total number of loads ignored due to invalid addresses
< Stats::Vector<> inv_addr_loads;
---
> /** Total number of loads forwaded from LSQ stores. */
> Stats::Scalar<> lsqForwLoads;
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< // total number of software prefetches ignored due to invalid addresses
< Stats::Vector<> inv_addr_swpfs;
---
> /** Total number of loads ignored due to invalid addresses. */
> Stats::Scalar<> invAddrLoads;
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< // total non-speculative bogus addresses seen (debug var)
< Counter sim_invalid_addrs;
< Stats::Vector<> fu_busy; //cumulative fu busy
---
> /** Total number of squashed loads. */
> Stats::Scalar<> lsqSquashedLoads;
460,461c456,458
< // ready loads blocked due to memory disambiguation
< Stats::Vector<> lsq_blocked_loads;
---
> /** Total number of responses from the memory system that are
> * ignored due to the instruction already being squashed. */
> Stats::Scalar<> lsqIgnoredResponses;
463,464c460,474
< Stats::Scalar<> lsqInversion;
< */
---
> /** Total number of squashed stores. */
> Stats::Scalar<> lsqSquashedStores;
>
> /** Total number of software prefetches ignored due to invalid addresses. */
> Stats::Scalar<> invAddrSwpfs;
>
> /** Ready loads blocked due to partial store-forwarding. */
> Stats::Scalar<> lsqBlockedLoads;
>
> /** Number of loads that were rescheduled. */
> Stats::Scalar<> lsqRescheduledLoads;
>
> /** Number of times the LSQ is blocked due to the cache. */
> Stats::Scalar<> lsqCacheBlocked;
>
521a532
> ++lsqRescheduledLoads;
601c612
< // Should keep track of stat for forwarded data
---
> ++lsqForwLoads;
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> ++lsqRescheduledLoads;
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> ++lsqBlockedLoads;
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> ++lsqCacheBlocked;