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< //#include "mem/page_table.hh"
< //#include "sim/debug.hh"
< //#include "sim/sim_object.hh"
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< /** Sets the page table pointer. */
< // void setPageTable(PageTable *pt_ptr);
<
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> /** Writes back the instruction, sending it to IEW. */
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> /** Handles completing the send of a store to memory. */
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> /** Pointer to memory object. */
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> /** DcachePort class for this LSQ Unit. Handles doing the
> * communication with the cache/memory.
> * @todo: Needs to be moved to the LSQ level and have some sort
> * of arbitration.
> */
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> /** Pointer to CPU. */
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> /** Pointer to LSQ. */
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> /** Default constructor. */
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> /** Atomic version of receive. Panics. */
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> /** Functional version of receive. Panics. */
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> /** Receives status change. Other than range changing, panics. */
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> /** Returns the address ranges of this device. */
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> /** Timing version of receive. Handles writing back and
> * completing the load or store that has returned from
> * memory. */
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> /** Handles doing a retry of the previous send. */
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> /** Derived class to hold any sender state the LSQ needs. */
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> /** Default constructor. */
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< // protected:
---
> /** Instruction who initiated the access to memory. */
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> /** Whether or not it is a load. */
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> /** The LQ/SQ index of the instruction. */
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> /** Whether or not the instruction will need to writeback. */
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< /** Pointer to the page table. */
< // PageTable *pTable;
<
---
> /** Writeback event, specifically for when stores forward data to loads. */
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> /** Instruction whose results are being written back. */
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> /** The packet that would have been sent to memory. */
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< PacketPtr sendingPkt;
---
> /** The packet that needs to be retried. */
> PacketPtr retryPkt;
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> /** Whehter or not a store is blocked due to the memory system. */