1/*
| 1/*
|
2 * Copyright (c) 2012 ARM Limited
| 2 * Copyright (c) 2012-2013 ARM Limited
|
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#ifndef __CPU_O3_LSQ_UNIT_HH__
45#define __CPU_O3_LSQ_UNIT_HH__
46
47#include <algorithm>
48#include <cstring>
49#include <map>
50#include <queue>
51
52#include "arch/generic/debugfaults.hh"
53#include "arch/isa_traits.hh"
54#include "arch/locked_mem.hh"
55#include "arch/mmapped_ipr.hh"
56#include "base/hashmap.hh"
57#include "config/the_isa.hh"
58#include "cpu/inst_seq.hh"
59#include "cpu/timebuf.hh"
60#include "debug/LSQUnit.hh"
61#include "mem/packet.hh"
62#include "mem/port.hh"
63#include "sim/fault_fwd.hh"
64
65struct DerivO3CPUParams;
66
67/**
68 * Class that implements the actual LQ and SQ for each specific
69 * thread. Both are circular queues; load entries are freed upon
70 * committing, while store entries are freed once they writeback. The
71 * LSQUnit tracks if there are memory ordering violations, and also
72 * detects partial load to store forwarding cases (a store only has
73 * part of a load's data) that requires the load to wait until the
74 * store writes back. In the former case it holds onto the instruction
75 * until the dependence unit looks at it, and in the latter it stalls
76 * the LSQ until the store writes back. At that point the load is
77 * replayed.
78 */
79template <class Impl>
80class LSQUnit {
81 public:
82 typedef typename Impl::O3CPU O3CPU;
83 typedef typename Impl::DynInstPtr DynInstPtr;
84 typedef typename Impl::CPUPol::IEW IEW;
85 typedef typename Impl::CPUPol::LSQ LSQ;
86 typedef typename Impl::CPUPol::IssueStruct IssueStruct;
87
88 public:
89 /** Constructs an LSQ unit. init() must be called prior to use. */
90 LSQUnit();
91
92 /** Initializes the LSQ unit with the specified number of entries. */
93 void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
94 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
95 unsigned id);
96
97 /** Returns the name of the LSQ unit. */
98 std::string name() const;
99
100 /** Registers statistics. */
101 void regStats();
102
103 /** Sets the pointer to the dcache port. */
104 void setDcachePort(MasterPort *dcache_port);
105
106 /** Perform sanity checks after a drain. */
107 void drainSanityCheck() const;
108
109 /** Takes over from another CPU's thread. */
110 void takeOverFrom();
111
112 /** Ticks the LSQ unit, which in this case only resets the number of
113 * used cache ports.
114 * @todo: Move the number of used ports up to the LSQ level so it can
115 * be shared by all LSQ units.
116 */
117 void tick() { usedPorts = 0; }
118
119 /** Inserts an instruction. */
120 void insert(DynInstPtr &inst);
121 /** Inserts a load instruction. */
122 void insertLoad(DynInstPtr &load_inst);
123 /** Inserts a store instruction. */
124 void insertStore(DynInstPtr &store_inst);
125
126 /** Check for ordering violations in the LSQ. For a store squash if we
127 * ever find a conflicting load. For a load, only squash if we
128 * an external snoop invalidate has been seen for that load address
129 * @param load_idx index to start checking at
130 * @param inst the instruction to check
131 */
132 Fault checkViolations(int load_idx, DynInstPtr &inst);
133
134 /** Check if an incoming invalidate hits in the lsq on a load
135 * that might have issued out of order wrt another load beacuse
136 * of the intermediate invalidate.
137 */
138 void checkSnoop(PacketPtr pkt);
139
140 /** Executes a load instruction. */
141 Fault executeLoad(DynInstPtr &inst);
142
143 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
144 /** Executes a store instruction. */
145 Fault executeStore(DynInstPtr &inst);
146
147 /** Commits the head load. */
148 void commitLoad();
149 /** Commits loads older than a specific sequence number. */
150 void commitLoads(InstSeqNum &youngest_inst);
151
152 /** Commits stores older than a specific sequence number. */
153 void commitStores(InstSeqNum &youngest_inst);
154
155 /** Writes back stores. */
156 void writebackStores();
157
158 /** Completes the data access that has been returned from the
159 * memory system. */
160 void completeDataAccess(PacketPtr pkt);
161
162 /** Clears all the entries in the LQ. */
163 void clearLQ();
164
165 /** Clears all the entries in the SQ. */
166 void clearSQ();
167
168 /** Resizes the LQ to a given size. */
169 void resizeLQ(unsigned size);
170
171 /** Resizes the SQ to a given size. */
172 void resizeSQ(unsigned size);
173
174 /** Squashes all instructions younger than a specific sequence number. */
175 void squash(const InstSeqNum &squashed_num);
176
177 /** Returns if there is a memory ordering violation. Value is reset upon
178 * call to getMemDepViolator().
179 */
180 bool violation() { return memDepViolator; }
181
182 /** Returns the memory ordering violator. */
183 DynInstPtr getMemDepViolator();
184
185 /** Returns if a load became blocked due to the memory system. */
186 bool loadBlocked()
187 { return isLoadBlocked; }
188
189 /** Clears the signal that a load became blocked. */
190 void clearLoadBlocked()
191 { isLoadBlocked = false; }
192
193 /** Returns if the blocked load was handled. */
194 bool isLoadBlockedHandled()
195 { return loadBlockedHandled; }
196
197 /** Records the blocked load as being handled. */
198 void setLoadBlockedHandled()
199 { loadBlockedHandled = true; }
200
201 /** Returns the number of free entries (min of free LQ and SQ entries). */
202 unsigned numFreeEntries();
203
204 /** Returns the number of loads in the LQ. */
205 int numLoads() { return loads; }
206
207 /** Returns the number of stores in the SQ. */
208 int numStores() { return stores; }
209
210 /** Returns if either the LQ or SQ is full. */
211 bool isFull() { return lqFull() || sqFull(); }
212
213 /** Returns if both the LQ and SQ are empty. */
214 bool isEmpty() const { return lqEmpty() && sqEmpty(); }
215
216 /** Returns if the LQ is full. */
217 bool lqFull() { return loads >= (LQEntries - 1); }
218
219 /** Returns if the SQ is full. */
220 bool sqFull() { return stores >= (SQEntries - 1); }
221
222 /** Returns if the LQ is empty. */
223 bool lqEmpty() const { return loads == 0; }
224
225 /** Returns if the SQ is empty. */
226 bool sqEmpty() const { return stores == 0; }
227
228 /** Returns the number of instructions in the LSQ. */
229 unsigned getCount() { return loads + stores; }
230
231 /** Returns if there are any stores to writeback. */
232 bool hasStoresToWB() { return storesToWB; }
233
234 /** Returns the number of stores to writeback. */
235 int numStoresToWB() { return storesToWB; }
236
237 /** Returns if the LSQ unit will writeback on this cycle. */
238 bool willWB() { return storeQueue[storeWBIdx].canWB &&
239 !storeQueue[storeWBIdx].completed &&
240 !isStoreBlocked; }
241
242 /** Handles doing the retry. */
243 void recvRetry();
244
245 private:
246 /** Reset the LSQ state */
247 void resetState();
248
249 /** Writes back the instruction, sending it to IEW. */
250 void writeback(DynInstPtr &inst, PacketPtr pkt);
251
252 /** Writes back a store that couldn't be completed the previous cycle. */
253 void writebackPendingStore();
254
255 /** Handles completing the send of a store to memory. */
256 void storePostSend(PacketPtr pkt);
257
258 /** Completes the store at the specified index. */
259 void completeStore(int store_idx);
260
261 /** Attempts to send a store to the cache. */
262 bool sendStore(PacketPtr data_pkt);
263
264 /** Increments the given store index (circular queue). */
265 inline void incrStIdx(int &store_idx) const;
266 /** Decrements the given store index (circular queue). */
267 inline void decrStIdx(int &store_idx) const;
268 /** Increments the given load index (circular queue). */
269 inline void incrLdIdx(int &load_idx) const;
270 /** Decrements the given load index (circular queue). */
271 inline void decrLdIdx(int &load_idx) const;
272
273 public:
274 /** Debugging function to dump instructions in the LSQ. */
275 void dumpInsts() const;
276
277 private:
278 /** Pointer to the CPU. */
279 O3CPU *cpu;
280
281 /** Pointer to the IEW stage. */
282 IEW *iewStage;
283
284 /** Pointer to the LSQ. */
285 LSQ *lsq;
286
287 /** Pointer to the dcache port. Used only for sending. */
288 MasterPort *dcachePort;
289
290 /** Derived class to hold any sender state the LSQ needs. */
291 class LSQSenderState : public Packet::SenderState
292 {
293 public:
294 /** Default constructor. */
295 LSQSenderState()
296 : mainPkt(NULL), pendingPacket(NULL), outstanding(1),
297 noWB(false), isSplit(false), pktToSend(false)
298 { }
299
300 /** Instruction who initiated the access to memory. */
301 DynInstPtr inst;
302 /** The main packet from a split load, used during writeback. */
303 PacketPtr mainPkt;
304 /** A second packet from a split store that needs sending. */
305 PacketPtr pendingPacket;
306 /** The LQ/SQ index of the instruction. */
307 uint8_t idx;
308 /** Number of outstanding packets to complete. */
309 uint8_t outstanding;
310 /** Whether or not it is a load. */
311 bool isLoad;
312 /** Whether or not the instruction will need to writeback. */
313 bool noWB;
314 /** Whether or not this access is split in two. */
315 bool isSplit;
316 /** Whether or not there is a packet that needs sending. */
317 bool pktToSend;
318
319 /** Completes a packet and returns whether the access is finished. */
320 inline bool complete() { return --outstanding == 0; }
321 };
322
323 /** Writeback event, specifically for when stores forward data to loads. */
324 class WritebackEvent : public Event {
325 public:
326 /** Constructs a writeback event. */
327 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr);
328
329 /** Processes the writeback event. */
330 void process();
331
332 /** Returns the description of this event. */
333 const char *description() const;
334
335 private:
336 /** Instruction whose results are being written back. */
337 DynInstPtr inst;
338
339 /** The packet that would have been sent to memory. */
340 PacketPtr pkt;
341
342 /** The pointer to the LSQ unit that issued the store. */
343 LSQUnit<Impl> *lsqPtr;
344 };
345
346 public:
347 struct SQEntry {
348 /** Constructs an empty store queue entry. */
349 SQEntry()
350 : inst(NULL), req(NULL), size(0),
351 canWB(0), committed(0), completed(0)
352 {
353 std::memset(data, 0, sizeof(data));
354 }
355
356 ~SQEntry()
357 {
358 inst = NULL;
359 }
360
361 /** Constructs a store queue entry for a given instruction. */
362 SQEntry(DynInstPtr &_inst)
363 : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0),
| 3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#ifndef __CPU_O3_LSQ_UNIT_HH__
45#define __CPU_O3_LSQ_UNIT_HH__
46
47#include <algorithm>
48#include <cstring>
49#include <map>
50#include <queue>
51
52#include "arch/generic/debugfaults.hh"
53#include "arch/isa_traits.hh"
54#include "arch/locked_mem.hh"
55#include "arch/mmapped_ipr.hh"
56#include "base/hashmap.hh"
57#include "config/the_isa.hh"
58#include "cpu/inst_seq.hh"
59#include "cpu/timebuf.hh"
60#include "debug/LSQUnit.hh"
61#include "mem/packet.hh"
62#include "mem/port.hh"
63#include "sim/fault_fwd.hh"
64
65struct DerivO3CPUParams;
66
67/**
68 * Class that implements the actual LQ and SQ for each specific
69 * thread. Both are circular queues; load entries are freed upon
70 * committing, while store entries are freed once they writeback. The
71 * LSQUnit tracks if there are memory ordering violations, and also
72 * detects partial load to store forwarding cases (a store only has
73 * part of a load's data) that requires the load to wait until the
74 * store writes back. In the former case it holds onto the instruction
75 * until the dependence unit looks at it, and in the latter it stalls
76 * the LSQ until the store writes back. At that point the load is
77 * replayed.
78 */
79template <class Impl>
80class LSQUnit {
81 public:
82 typedef typename Impl::O3CPU O3CPU;
83 typedef typename Impl::DynInstPtr DynInstPtr;
84 typedef typename Impl::CPUPol::IEW IEW;
85 typedef typename Impl::CPUPol::LSQ LSQ;
86 typedef typename Impl::CPUPol::IssueStruct IssueStruct;
87
88 public:
89 /** Constructs an LSQ unit. init() must be called prior to use. */
90 LSQUnit();
91
92 /** Initializes the LSQ unit with the specified number of entries. */
93 void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
94 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
95 unsigned id);
96
97 /** Returns the name of the LSQ unit. */
98 std::string name() const;
99
100 /** Registers statistics. */
101 void regStats();
102
103 /** Sets the pointer to the dcache port. */
104 void setDcachePort(MasterPort *dcache_port);
105
106 /** Perform sanity checks after a drain. */
107 void drainSanityCheck() const;
108
109 /** Takes over from another CPU's thread. */
110 void takeOverFrom();
111
112 /** Ticks the LSQ unit, which in this case only resets the number of
113 * used cache ports.
114 * @todo: Move the number of used ports up to the LSQ level so it can
115 * be shared by all LSQ units.
116 */
117 void tick() { usedPorts = 0; }
118
119 /** Inserts an instruction. */
120 void insert(DynInstPtr &inst);
121 /** Inserts a load instruction. */
122 void insertLoad(DynInstPtr &load_inst);
123 /** Inserts a store instruction. */
124 void insertStore(DynInstPtr &store_inst);
125
126 /** Check for ordering violations in the LSQ. For a store squash if we
127 * ever find a conflicting load. For a load, only squash if we
128 * an external snoop invalidate has been seen for that load address
129 * @param load_idx index to start checking at
130 * @param inst the instruction to check
131 */
132 Fault checkViolations(int load_idx, DynInstPtr &inst);
133
134 /** Check if an incoming invalidate hits in the lsq on a load
135 * that might have issued out of order wrt another load beacuse
136 * of the intermediate invalidate.
137 */
138 void checkSnoop(PacketPtr pkt);
139
140 /** Executes a load instruction. */
141 Fault executeLoad(DynInstPtr &inst);
142
143 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
144 /** Executes a store instruction. */
145 Fault executeStore(DynInstPtr &inst);
146
147 /** Commits the head load. */
148 void commitLoad();
149 /** Commits loads older than a specific sequence number. */
150 void commitLoads(InstSeqNum &youngest_inst);
151
152 /** Commits stores older than a specific sequence number. */
153 void commitStores(InstSeqNum &youngest_inst);
154
155 /** Writes back stores. */
156 void writebackStores();
157
158 /** Completes the data access that has been returned from the
159 * memory system. */
160 void completeDataAccess(PacketPtr pkt);
161
162 /** Clears all the entries in the LQ. */
163 void clearLQ();
164
165 /** Clears all the entries in the SQ. */
166 void clearSQ();
167
168 /** Resizes the LQ to a given size. */
169 void resizeLQ(unsigned size);
170
171 /** Resizes the SQ to a given size. */
172 void resizeSQ(unsigned size);
173
174 /** Squashes all instructions younger than a specific sequence number. */
175 void squash(const InstSeqNum &squashed_num);
176
177 /** Returns if there is a memory ordering violation. Value is reset upon
178 * call to getMemDepViolator().
179 */
180 bool violation() { return memDepViolator; }
181
182 /** Returns the memory ordering violator. */
183 DynInstPtr getMemDepViolator();
184
185 /** Returns if a load became blocked due to the memory system. */
186 bool loadBlocked()
187 { return isLoadBlocked; }
188
189 /** Clears the signal that a load became blocked. */
190 void clearLoadBlocked()
191 { isLoadBlocked = false; }
192
193 /** Returns if the blocked load was handled. */
194 bool isLoadBlockedHandled()
195 { return loadBlockedHandled; }
196
197 /** Records the blocked load as being handled. */
198 void setLoadBlockedHandled()
199 { loadBlockedHandled = true; }
200
201 /** Returns the number of free entries (min of free LQ and SQ entries). */
202 unsigned numFreeEntries();
203
204 /** Returns the number of loads in the LQ. */
205 int numLoads() { return loads; }
206
207 /** Returns the number of stores in the SQ. */
208 int numStores() { return stores; }
209
210 /** Returns if either the LQ or SQ is full. */
211 bool isFull() { return lqFull() || sqFull(); }
212
213 /** Returns if both the LQ and SQ are empty. */
214 bool isEmpty() const { return lqEmpty() && sqEmpty(); }
215
216 /** Returns if the LQ is full. */
217 bool lqFull() { return loads >= (LQEntries - 1); }
218
219 /** Returns if the SQ is full. */
220 bool sqFull() { return stores >= (SQEntries - 1); }
221
222 /** Returns if the LQ is empty. */
223 bool lqEmpty() const { return loads == 0; }
224
225 /** Returns if the SQ is empty. */
226 bool sqEmpty() const { return stores == 0; }
227
228 /** Returns the number of instructions in the LSQ. */
229 unsigned getCount() { return loads + stores; }
230
231 /** Returns if there are any stores to writeback. */
232 bool hasStoresToWB() { return storesToWB; }
233
234 /** Returns the number of stores to writeback. */
235 int numStoresToWB() { return storesToWB; }
236
237 /** Returns if the LSQ unit will writeback on this cycle. */
238 bool willWB() { return storeQueue[storeWBIdx].canWB &&
239 !storeQueue[storeWBIdx].completed &&
240 !isStoreBlocked; }
241
242 /** Handles doing the retry. */
243 void recvRetry();
244
245 private:
246 /** Reset the LSQ state */
247 void resetState();
248
249 /** Writes back the instruction, sending it to IEW. */
250 void writeback(DynInstPtr &inst, PacketPtr pkt);
251
252 /** Writes back a store that couldn't be completed the previous cycle. */
253 void writebackPendingStore();
254
255 /** Handles completing the send of a store to memory. */
256 void storePostSend(PacketPtr pkt);
257
258 /** Completes the store at the specified index. */
259 void completeStore(int store_idx);
260
261 /** Attempts to send a store to the cache. */
262 bool sendStore(PacketPtr data_pkt);
263
264 /** Increments the given store index (circular queue). */
265 inline void incrStIdx(int &store_idx) const;
266 /** Decrements the given store index (circular queue). */
267 inline void decrStIdx(int &store_idx) const;
268 /** Increments the given load index (circular queue). */
269 inline void incrLdIdx(int &load_idx) const;
270 /** Decrements the given load index (circular queue). */
271 inline void decrLdIdx(int &load_idx) const;
272
273 public:
274 /** Debugging function to dump instructions in the LSQ. */
275 void dumpInsts() const;
276
277 private:
278 /** Pointer to the CPU. */
279 O3CPU *cpu;
280
281 /** Pointer to the IEW stage. */
282 IEW *iewStage;
283
284 /** Pointer to the LSQ. */
285 LSQ *lsq;
286
287 /** Pointer to the dcache port. Used only for sending. */
288 MasterPort *dcachePort;
289
290 /** Derived class to hold any sender state the LSQ needs. */
291 class LSQSenderState : public Packet::SenderState
292 {
293 public:
294 /** Default constructor. */
295 LSQSenderState()
296 : mainPkt(NULL), pendingPacket(NULL), outstanding(1),
297 noWB(false), isSplit(false), pktToSend(false)
298 { }
299
300 /** Instruction who initiated the access to memory. */
301 DynInstPtr inst;
302 /** The main packet from a split load, used during writeback. */
303 PacketPtr mainPkt;
304 /** A second packet from a split store that needs sending. */
305 PacketPtr pendingPacket;
306 /** The LQ/SQ index of the instruction. */
307 uint8_t idx;
308 /** Number of outstanding packets to complete. */
309 uint8_t outstanding;
310 /** Whether or not it is a load. */
311 bool isLoad;
312 /** Whether or not the instruction will need to writeback. */
313 bool noWB;
314 /** Whether or not this access is split in two. */
315 bool isSplit;
316 /** Whether or not there is a packet that needs sending. */
317 bool pktToSend;
318
319 /** Completes a packet and returns whether the access is finished. */
320 inline bool complete() { return --outstanding == 0; }
321 };
322
323 /** Writeback event, specifically for when stores forward data to loads. */
324 class WritebackEvent : public Event {
325 public:
326 /** Constructs a writeback event. */
327 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr);
328
329 /** Processes the writeback event. */
330 void process();
331
332 /** Returns the description of this event. */
333 const char *description() const;
334
335 private:
336 /** Instruction whose results are being written back. */
337 DynInstPtr inst;
338
339 /** The packet that would have been sent to memory. */
340 PacketPtr pkt;
341
342 /** The pointer to the LSQ unit that issued the store. */
343 LSQUnit<Impl> *lsqPtr;
344 };
345
346 public:
347 struct SQEntry {
348 /** Constructs an empty store queue entry. */
349 SQEntry()
350 : inst(NULL), req(NULL), size(0),
351 canWB(0), committed(0), completed(0)
352 {
353 std::memset(data, 0, sizeof(data));
354 }
355
356 ~SQEntry()
357 {
358 inst = NULL;
359 }
360
361 /** Constructs a store queue entry for a given instruction. */
362 SQEntry(DynInstPtr &_inst)
363 : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0),
|
364 isSplit(0), canWB(0), committed(0), completed(0)
| 364 isSplit(0), canWB(0), committed(0), completed(0), isAllZeros(0)
|
365 {
366 std::memset(data, 0, sizeof(data));
367 }
368 /** The store data. */
369 char data[16];
370 /** The store instruction. */
371 DynInstPtr inst;
372 /** The request for the store. */
373 RequestPtr req;
374 /** The split requests for the store. */
375 RequestPtr sreqLow;
376 RequestPtr sreqHigh;
377 /** The size of the store. */
378 uint8_t size;
379 /** Whether or not the store is split into two requests. */
380 bool isSplit;
381 /** Whether or not the store can writeback. */
382 bool canWB;
383 /** Whether or not the store is committed. */
384 bool committed;
385 /** Whether or not the store is completed. */
386 bool completed;
| 365 {
366 std::memset(data, 0, sizeof(data));
367 }
368 /** The store data. */
369 char data[16];
370 /** The store instruction. */
371 DynInstPtr inst;
372 /** The request for the store. */
373 RequestPtr req;
374 /** The split requests for the store. */
375 RequestPtr sreqLow;
376 RequestPtr sreqHigh;
377 /** The size of the store. */
378 uint8_t size;
379 /** Whether or not the store is split into two requests. */
380 bool isSplit;
381 /** Whether or not the store can writeback. */
382 bool canWB;
383 /** Whether or not the store is committed. */
384 bool committed;
385 /** Whether or not the store is completed. */
386 bool completed;
|
| 387 /** Does this request write all zeros and thus doesn't
388 * have any data attached to it. Used for cache block zero
389 * style instructs (ARM DC ZVA; ALPHA WH64)
390 */
391 bool isAllZeros;
|
387 };
388
389 private:
390 /** The LSQUnit thread id. */
391 ThreadID lsqID;
392
393 /** The store queue. */
394 std::vector<SQEntry> storeQueue;
395
396 /** The load queue. */
397 std::vector<DynInstPtr> loadQueue;
398
399 /** The number of LQ entries, plus a sentinel entry (circular queue).
400 * @todo: Consider having var that records the true number of LQ entries.
401 */
402 unsigned LQEntries;
403 /** The number of SQ entries, plus a sentinel entry (circular queue).
404 * @todo: Consider having var that records the true number of SQ entries.
405 */
406 unsigned SQEntries;
407
408 /** The number of places to shift addresses in the LSQ before checking
409 * for dependency violations
410 */
411 unsigned depCheckShift;
412
413 /** Should loads be checked for dependency issues */
414 bool checkLoads;
415
416 /** The number of load instructions in the LQ. */
417 int loads;
418 /** The number of store instructions in the SQ. */
419 int stores;
420 /** The number of store instructions in the SQ waiting to writeback. */
421 int storesToWB;
422
423 /** The index of the head instruction in the LQ. */
424 int loadHead;
425 /** The index of the tail instruction in the LQ. */
426 int loadTail;
427
428 /** The index of the head instruction in the SQ. */
429 int storeHead;
430 /** The index of the first instruction that may be ready to be
431 * written back, and has not yet been written back.
432 */
433 int storeWBIdx;
434 /** The index of the tail instruction in the SQ. */
435 int storeTail;
436
437 /// @todo Consider moving to a more advanced model with write vs read ports
438 /** The number of cache ports available each cycle. */
439 int cachePorts;
440
441 /** The number of used cache ports in this cycle. */
442 int usedPorts;
443
444 //list<InstSeqNum> mshrSeqNums;
445
446 /** Address Mask for a cache block (e.g. ~(cache_block_size-1)) */
447 Addr cacheBlockMask;
448
449 /** Wire to read information from the issue stage time queue. */
450 typename TimeBuffer<IssueStruct>::wire fromIssue;
451
452 /** Whether or not the LSQ is stalled. */
453 bool stalled;
454 /** The store that causes the stall due to partial store to load
455 * forwarding.
456 */
457 InstSeqNum stallingStoreIsn;
458 /** The index of the above store. */
459 int stallingLoadIdx;
460
461 /** The packet that needs to be retried. */
462 PacketPtr retryPkt;
463
464 /** Whehter or not a store is blocked due to the memory system. */
465 bool isStoreBlocked;
466
467 /** Whether or not a load is blocked due to the memory system. */
468 bool isLoadBlocked;
469
470 /** Has the blocked load been handled. */
471 bool loadBlockedHandled;
472
473 /** Whether or not a store is in flight. */
474 bool storeInFlight;
475
476 /** The sequence number of the blocked load. */
477 InstSeqNum blockedLoadSeqNum;
478
479 /** The oldest load that caused a memory ordering violation. */
480 DynInstPtr memDepViolator;
481
482 /** Whether or not there is a packet that couldn't be sent because of
483 * a lack of cache ports. */
484 bool hasPendingPkt;
485
486 /** The packet that is pending free cache ports. */
487 PacketPtr pendingPkt;
488
489 /** Flag for memory model. */
490 bool needsTSO;
491
492 // Will also need how many read/write ports the Dcache has. Or keep track
493 // of that in stage that is one level up, and only call executeLoad/Store
494 // the appropriate number of times.
495 /** Total number of loads forwaded from LSQ stores. */
496 Stats::Scalar lsqForwLoads;
497
498 /** Total number of loads ignored due to invalid addresses. */
499 Stats::Scalar invAddrLoads;
500
501 /** Total number of squashed loads. */
502 Stats::Scalar lsqSquashedLoads;
503
504 /** Total number of responses from the memory system that are
505 * ignored due to the instruction already being squashed. */
506 Stats::Scalar lsqIgnoredResponses;
507
508 /** Tota number of memory ordering violations. */
509 Stats::Scalar lsqMemOrderViolation;
510
511 /** Total number of squashed stores. */
512 Stats::Scalar lsqSquashedStores;
513
514 /** Total number of software prefetches ignored due to invalid addresses. */
515 Stats::Scalar invAddrSwpfs;
516
517 /** Ready loads blocked due to partial store-forwarding. */
518 Stats::Scalar lsqBlockedLoads;
519
520 /** Number of loads that were rescheduled. */
521 Stats::Scalar lsqRescheduledLoads;
522
523 /** Number of times the LSQ is blocked due to the cache. */
524 Stats::Scalar lsqCacheBlocked;
525
526 public:
527 /** Executes the load at the given index. */
528 Fault read(Request *req, Request *sreqLow, Request *sreqHigh,
529 uint8_t *data, int load_idx);
530
531 /** Executes the store at the given index. */
532 Fault write(Request *req, Request *sreqLow, Request *sreqHigh,
533 uint8_t *data, int store_idx);
534
535 /** Returns the index of the head load instruction. */
536 int getLoadHead() { return loadHead; }
537 /** Returns the sequence number of the head load instruction. */
538 InstSeqNum getLoadHeadSeqNum()
539 {
540 if (loadQueue[loadHead]) {
541 return loadQueue[loadHead]->seqNum;
542 } else {
543 return 0;
544 }
545
546 }
547
548 /** Returns the index of the head store instruction. */
549 int getStoreHead() { return storeHead; }
550 /** Returns the sequence number of the head store instruction. */
551 InstSeqNum getStoreHeadSeqNum()
552 {
553 if (storeQueue[storeHead].inst) {
554 return storeQueue[storeHead].inst->seqNum;
555 } else {
556 return 0;
557 }
558
559 }
560
561 /** Returns whether or not the LSQ unit is stalled. */
562 bool isStalled() { return stalled; }
563};
564
565template <class Impl>
566Fault
567LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
568 uint8_t *data, int load_idx)
569{
570 DynInstPtr load_inst = loadQueue[load_idx];
571
572 assert(load_inst);
573
574 assert(!load_inst->isExecuted());
575
576 // Make sure this isn't an uncacheable access
577 // A bit of a hackish way to get uncached accesses to work only if they're
578 // at the head of the LSQ and are ready to commit (at the head of the ROB
579 // too).
580 if (req->isUncacheable() &&
581 (load_idx != loadHead || !load_inst->isAtCommit())) {
582 iewStage->rescheduleMemInst(load_inst);
583 ++lsqRescheduledLoads;
584 DPRINTF(LSQUnit, "Uncachable load [sn:%lli] PC %s\n",
585 load_inst->seqNum, load_inst->pcState());
586
587 // Must delete request now that it wasn't handed off to
588 // memory. This is quite ugly. @todo: Figure out the proper
589 // place to really handle request deletes.
590 delete req;
591 if (TheISA::HasUnalignedMemAcc && sreqLow) {
592 delete sreqLow;
593 delete sreqHigh;
594 }
595 return new GenericISA::M5PanicFault(
596 "Uncachable load [sn:%llx] PC %s\n",
597 load_inst->seqNum, load_inst->pcState());
598 }
599
600 // Check the SQ for any previous stores that might lead to forwarding
601 int store_idx = load_inst->sqIdx;
602
603 int store_size = 0;
604
605 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
606 "storeHead: %i addr: %#x%s\n",
607 load_idx, store_idx, storeHead, req->getPaddr(),
608 sreqLow ? " split" : "");
609
610 if (req->isLLSC()) {
611 assert(!sreqLow);
612 // Disable recording the result temporarily. Writing to misc
613 // regs normally updates the result, but this is not the
614 // desired behavior when handling store conditionals.
615 load_inst->recordResult(false);
616 TheISA::handleLockedRead(load_inst.get(), req);
617 load_inst->recordResult(true);
618 }
619
620 if (req->isMmappedIpr()) {
621 assert(!load_inst->memData);
622 load_inst->memData = new uint8_t[64];
623
624 ThreadContext *thread = cpu->tcBase(lsqID);
625 Cycles delay(0);
626 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
627
628 if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
629 data_pkt->dataStatic(load_inst->memData);
630 delay = TheISA::handleIprRead(thread, data_pkt);
631 } else {
632 assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr());
633 PacketPtr fst_data_pkt = new Packet(sreqLow, MemCmd::ReadReq);
634 PacketPtr snd_data_pkt = new Packet(sreqHigh, MemCmd::ReadReq);
635
636 fst_data_pkt->dataStatic(load_inst->memData);
637 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
638
639 delay = TheISA::handleIprRead(thread, fst_data_pkt);
640 Cycles delay2 = TheISA::handleIprRead(thread, snd_data_pkt);
641 if (delay2 > delay)
642 delay = delay2;
643
644 delete sreqLow;
645 delete sreqHigh;
646 delete fst_data_pkt;
647 delete snd_data_pkt;
648 }
649 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
650 cpu->schedule(wb, cpu->clockEdge(delay));
651 return NoFault;
652 }
653
654 while (store_idx != -1) {
655 // End once we've reached the top of the LSQ
656 if (store_idx == storeWBIdx) {
657 break;
658 }
659
660 // Move the index to one younger
661 if (--store_idx < 0)
662 store_idx += SQEntries;
663
664 assert(storeQueue[store_idx].inst);
665
666 store_size = storeQueue[store_idx].size;
667
668 if (store_size == 0)
669 continue;
670 else if (storeQueue[store_idx].inst->uncacheable())
671 continue;
672
673 assert(storeQueue[store_idx].inst->effAddrValid());
674
675 // Check if the store data is within the lower and upper bounds of
676 // addresses that the request needs.
677 bool store_has_lower_limit =
678 req->getVaddr() >= storeQueue[store_idx].inst->effAddr;
679 bool store_has_upper_limit =
680 (req->getVaddr() + req->getSize()) <=
681 (storeQueue[store_idx].inst->effAddr + store_size);
682 bool lower_load_has_store_part =
683 req->getVaddr() < (storeQueue[store_idx].inst->effAddr +
684 store_size);
685 bool upper_load_has_store_part =
686 (req->getVaddr() + req->getSize()) >
687 storeQueue[store_idx].inst->effAddr;
688
689 // If the store's data has all of the data needed, we can forward.
690 if ((store_has_lower_limit && store_has_upper_limit)) {
691 // Get shift amount for offset into the store's data.
692 int shift_amt = req->getVaddr() - storeQueue[store_idx].inst->effAddr;
693
| 392 };
393
394 private:
395 /** The LSQUnit thread id. */
396 ThreadID lsqID;
397
398 /** The store queue. */
399 std::vector<SQEntry> storeQueue;
400
401 /** The load queue. */
402 std::vector<DynInstPtr> loadQueue;
403
404 /** The number of LQ entries, plus a sentinel entry (circular queue).
405 * @todo: Consider having var that records the true number of LQ entries.
406 */
407 unsigned LQEntries;
408 /** The number of SQ entries, plus a sentinel entry (circular queue).
409 * @todo: Consider having var that records the true number of SQ entries.
410 */
411 unsigned SQEntries;
412
413 /** The number of places to shift addresses in the LSQ before checking
414 * for dependency violations
415 */
416 unsigned depCheckShift;
417
418 /** Should loads be checked for dependency issues */
419 bool checkLoads;
420
421 /** The number of load instructions in the LQ. */
422 int loads;
423 /** The number of store instructions in the SQ. */
424 int stores;
425 /** The number of store instructions in the SQ waiting to writeback. */
426 int storesToWB;
427
428 /** The index of the head instruction in the LQ. */
429 int loadHead;
430 /** The index of the tail instruction in the LQ. */
431 int loadTail;
432
433 /** The index of the head instruction in the SQ. */
434 int storeHead;
435 /** The index of the first instruction that may be ready to be
436 * written back, and has not yet been written back.
437 */
438 int storeWBIdx;
439 /** The index of the tail instruction in the SQ. */
440 int storeTail;
441
442 /// @todo Consider moving to a more advanced model with write vs read ports
443 /** The number of cache ports available each cycle. */
444 int cachePorts;
445
446 /** The number of used cache ports in this cycle. */
447 int usedPorts;
448
449 //list<InstSeqNum> mshrSeqNums;
450
451 /** Address Mask for a cache block (e.g. ~(cache_block_size-1)) */
452 Addr cacheBlockMask;
453
454 /** Wire to read information from the issue stage time queue. */
455 typename TimeBuffer<IssueStruct>::wire fromIssue;
456
457 /** Whether or not the LSQ is stalled. */
458 bool stalled;
459 /** The store that causes the stall due to partial store to load
460 * forwarding.
461 */
462 InstSeqNum stallingStoreIsn;
463 /** The index of the above store. */
464 int stallingLoadIdx;
465
466 /** The packet that needs to be retried. */
467 PacketPtr retryPkt;
468
469 /** Whehter or not a store is blocked due to the memory system. */
470 bool isStoreBlocked;
471
472 /** Whether or not a load is blocked due to the memory system. */
473 bool isLoadBlocked;
474
475 /** Has the blocked load been handled. */
476 bool loadBlockedHandled;
477
478 /** Whether or not a store is in flight. */
479 bool storeInFlight;
480
481 /** The sequence number of the blocked load. */
482 InstSeqNum blockedLoadSeqNum;
483
484 /** The oldest load that caused a memory ordering violation. */
485 DynInstPtr memDepViolator;
486
487 /** Whether or not there is a packet that couldn't be sent because of
488 * a lack of cache ports. */
489 bool hasPendingPkt;
490
491 /** The packet that is pending free cache ports. */
492 PacketPtr pendingPkt;
493
494 /** Flag for memory model. */
495 bool needsTSO;
496
497 // Will also need how many read/write ports the Dcache has. Or keep track
498 // of that in stage that is one level up, and only call executeLoad/Store
499 // the appropriate number of times.
500 /** Total number of loads forwaded from LSQ stores. */
501 Stats::Scalar lsqForwLoads;
502
503 /** Total number of loads ignored due to invalid addresses. */
504 Stats::Scalar invAddrLoads;
505
506 /** Total number of squashed loads. */
507 Stats::Scalar lsqSquashedLoads;
508
509 /** Total number of responses from the memory system that are
510 * ignored due to the instruction already being squashed. */
511 Stats::Scalar lsqIgnoredResponses;
512
513 /** Tota number of memory ordering violations. */
514 Stats::Scalar lsqMemOrderViolation;
515
516 /** Total number of squashed stores. */
517 Stats::Scalar lsqSquashedStores;
518
519 /** Total number of software prefetches ignored due to invalid addresses. */
520 Stats::Scalar invAddrSwpfs;
521
522 /** Ready loads blocked due to partial store-forwarding. */
523 Stats::Scalar lsqBlockedLoads;
524
525 /** Number of loads that were rescheduled. */
526 Stats::Scalar lsqRescheduledLoads;
527
528 /** Number of times the LSQ is blocked due to the cache. */
529 Stats::Scalar lsqCacheBlocked;
530
531 public:
532 /** Executes the load at the given index. */
533 Fault read(Request *req, Request *sreqLow, Request *sreqHigh,
534 uint8_t *data, int load_idx);
535
536 /** Executes the store at the given index. */
537 Fault write(Request *req, Request *sreqLow, Request *sreqHigh,
538 uint8_t *data, int store_idx);
539
540 /** Returns the index of the head load instruction. */
541 int getLoadHead() { return loadHead; }
542 /** Returns the sequence number of the head load instruction. */
543 InstSeqNum getLoadHeadSeqNum()
544 {
545 if (loadQueue[loadHead]) {
546 return loadQueue[loadHead]->seqNum;
547 } else {
548 return 0;
549 }
550
551 }
552
553 /** Returns the index of the head store instruction. */
554 int getStoreHead() { return storeHead; }
555 /** Returns the sequence number of the head store instruction. */
556 InstSeqNum getStoreHeadSeqNum()
557 {
558 if (storeQueue[storeHead].inst) {
559 return storeQueue[storeHead].inst->seqNum;
560 } else {
561 return 0;
562 }
563
564 }
565
566 /** Returns whether or not the LSQ unit is stalled. */
567 bool isStalled() { return stalled; }
568};
569
570template <class Impl>
571Fault
572LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
573 uint8_t *data, int load_idx)
574{
575 DynInstPtr load_inst = loadQueue[load_idx];
576
577 assert(load_inst);
578
579 assert(!load_inst->isExecuted());
580
581 // Make sure this isn't an uncacheable access
582 // A bit of a hackish way to get uncached accesses to work only if they're
583 // at the head of the LSQ and are ready to commit (at the head of the ROB
584 // too).
585 if (req->isUncacheable() &&
586 (load_idx != loadHead || !load_inst->isAtCommit())) {
587 iewStage->rescheduleMemInst(load_inst);
588 ++lsqRescheduledLoads;
589 DPRINTF(LSQUnit, "Uncachable load [sn:%lli] PC %s\n",
590 load_inst->seqNum, load_inst->pcState());
591
592 // Must delete request now that it wasn't handed off to
593 // memory. This is quite ugly. @todo: Figure out the proper
594 // place to really handle request deletes.
595 delete req;
596 if (TheISA::HasUnalignedMemAcc && sreqLow) {
597 delete sreqLow;
598 delete sreqHigh;
599 }
600 return new GenericISA::M5PanicFault(
601 "Uncachable load [sn:%llx] PC %s\n",
602 load_inst->seqNum, load_inst->pcState());
603 }
604
605 // Check the SQ for any previous stores that might lead to forwarding
606 int store_idx = load_inst->sqIdx;
607
608 int store_size = 0;
609
610 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
611 "storeHead: %i addr: %#x%s\n",
612 load_idx, store_idx, storeHead, req->getPaddr(),
613 sreqLow ? " split" : "");
614
615 if (req->isLLSC()) {
616 assert(!sreqLow);
617 // Disable recording the result temporarily. Writing to misc
618 // regs normally updates the result, but this is not the
619 // desired behavior when handling store conditionals.
620 load_inst->recordResult(false);
621 TheISA::handleLockedRead(load_inst.get(), req);
622 load_inst->recordResult(true);
623 }
624
625 if (req->isMmappedIpr()) {
626 assert(!load_inst->memData);
627 load_inst->memData = new uint8_t[64];
628
629 ThreadContext *thread = cpu->tcBase(lsqID);
630 Cycles delay(0);
631 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
632
633 if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
634 data_pkt->dataStatic(load_inst->memData);
635 delay = TheISA::handleIprRead(thread, data_pkt);
636 } else {
637 assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr());
638 PacketPtr fst_data_pkt = new Packet(sreqLow, MemCmd::ReadReq);
639 PacketPtr snd_data_pkt = new Packet(sreqHigh, MemCmd::ReadReq);
640
641 fst_data_pkt->dataStatic(load_inst->memData);
642 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
643
644 delay = TheISA::handleIprRead(thread, fst_data_pkt);
645 Cycles delay2 = TheISA::handleIprRead(thread, snd_data_pkt);
646 if (delay2 > delay)
647 delay = delay2;
648
649 delete sreqLow;
650 delete sreqHigh;
651 delete fst_data_pkt;
652 delete snd_data_pkt;
653 }
654 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
655 cpu->schedule(wb, cpu->clockEdge(delay));
656 return NoFault;
657 }
658
659 while (store_idx != -1) {
660 // End once we've reached the top of the LSQ
661 if (store_idx == storeWBIdx) {
662 break;
663 }
664
665 // Move the index to one younger
666 if (--store_idx < 0)
667 store_idx += SQEntries;
668
669 assert(storeQueue[store_idx].inst);
670
671 store_size = storeQueue[store_idx].size;
672
673 if (store_size == 0)
674 continue;
675 else if (storeQueue[store_idx].inst->uncacheable())
676 continue;
677
678 assert(storeQueue[store_idx].inst->effAddrValid());
679
680 // Check if the store data is within the lower and upper bounds of
681 // addresses that the request needs.
682 bool store_has_lower_limit =
683 req->getVaddr() >= storeQueue[store_idx].inst->effAddr;
684 bool store_has_upper_limit =
685 (req->getVaddr() + req->getSize()) <=
686 (storeQueue[store_idx].inst->effAddr + store_size);
687 bool lower_load_has_store_part =
688 req->getVaddr() < (storeQueue[store_idx].inst->effAddr +
689 store_size);
690 bool upper_load_has_store_part =
691 (req->getVaddr() + req->getSize()) >
692 storeQueue[store_idx].inst->effAddr;
693
694 // If the store's data has all of the data needed, we can forward.
695 if ((store_has_lower_limit && store_has_upper_limit)) {
696 // Get shift amount for offset into the store's data.
697 int shift_amt = req->getVaddr() - storeQueue[store_idx].inst->effAddr;
698
|
694 memcpy(data, storeQueue[store_idx].data + shift_amt,
| 699 if (storeQueue[store_idx].isAllZeros)
700 memset(data, 0, req->getSize());
701 else
702 memcpy(data, storeQueue[store_idx].data + shift_amt,
|
695 req->getSize());
696
697 assert(!load_inst->memData);
| 703 req->getSize());
704
705 assert(!load_inst->memData);
|
698 load_inst->memData = new uint8_t[64];
699
700 memcpy(load_inst->memData,
| 706 load_inst->memData = new uint8_t[req->getSize()];
707 if (storeQueue[store_idx].isAllZeros)
708 memset(load_inst->memData, 0, req->getSize());
709 else
710 memcpy(load_inst->memData,
|
701 storeQueue[store_idx].data + shift_amt, req->getSize());
702
703 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
704 "addr %#x, data %#x\n",
705 store_idx, req->getVaddr(), data);
706
707 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
708 data_pkt->dataStatic(load_inst->memData);
709
710 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
711
712 // We'll say this has a 1 cycle load-store forwarding latency
713 // for now.
714 // @todo: Need to make this a parameter.
715 cpu->schedule(wb, curTick());
716
717 // Don't need to do anything special for split loads.
718 if (TheISA::HasUnalignedMemAcc && sreqLow) {
719 delete sreqLow;
720 delete sreqHigh;
721 }
722
723 ++lsqForwLoads;
724 return NoFault;
725 } else if ((store_has_lower_limit && lower_load_has_store_part) ||
726 (store_has_upper_limit && upper_load_has_store_part) ||
727 (lower_load_has_store_part && upper_load_has_store_part)) {
728 // This is the partial store-load forwarding case where a store
729 // has only part of the load's data.
730
731 // If it's already been written back, then don't worry about
732 // stalling on it.
733 if (storeQueue[store_idx].completed) {
734 panic("Should not check one of these");
735 continue;
736 }
737
738 // Must stall load and force it to retry, so long as it's the oldest
739 // load that needs to do so.
740 if (!stalled ||
741 (stalled &&
742 load_inst->seqNum <
743 loadQueue[stallingLoadIdx]->seqNum)) {
744 stalled = true;
745 stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
746 stallingLoadIdx = load_idx;
747 }
748
749 // Tell IQ/mem dep unit that this instruction will need to be
750 // rescheduled eventually
751 iewStage->rescheduleMemInst(load_inst);
752 iewStage->decrWb(load_inst->seqNum);
753 load_inst->clearIssued();
754 ++lsqRescheduledLoads;
755
756 // Do not generate a writeback event as this instruction is not
757 // complete.
758 DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
759 "Store idx %i to load addr %#x\n",
760 store_idx, req->getVaddr());
761
762 // Must delete request now that it wasn't handed off to
763 // memory. This is quite ugly. @todo: Figure out the
764 // proper place to really handle request deletes.
765 delete req;
766 if (TheISA::HasUnalignedMemAcc && sreqLow) {
767 delete sreqLow;
768 delete sreqHigh;
769 }
770
771 return NoFault;
772 }
773 }
774
775 // If there's no forwarding case, then go access memory
776 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %s\n",
777 load_inst->seqNum, load_inst->pcState());
778
779 assert(!load_inst->memData);
| 711 storeQueue[store_idx].data + shift_amt, req->getSize());
712
713 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
714 "addr %#x, data %#x\n",
715 store_idx, req->getVaddr(), data);
716
717 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
718 data_pkt->dataStatic(load_inst->memData);
719
720 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
721
722 // We'll say this has a 1 cycle load-store forwarding latency
723 // for now.
724 // @todo: Need to make this a parameter.
725 cpu->schedule(wb, curTick());
726
727 // Don't need to do anything special for split loads.
728 if (TheISA::HasUnalignedMemAcc && sreqLow) {
729 delete sreqLow;
730 delete sreqHigh;
731 }
732
733 ++lsqForwLoads;
734 return NoFault;
735 } else if ((store_has_lower_limit && lower_load_has_store_part) ||
736 (store_has_upper_limit && upper_load_has_store_part) ||
737 (lower_load_has_store_part && upper_load_has_store_part)) {
738 // This is the partial store-load forwarding case where a store
739 // has only part of the load's data.
740
741 // If it's already been written back, then don't worry about
742 // stalling on it.
743 if (storeQueue[store_idx].completed) {
744 panic("Should not check one of these");
745 continue;
746 }
747
748 // Must stall load and force it to retry, so long as it's the oldest
749 // load that needs to do so.
750 if (!stalled ||
751 (stalled &&
752 load_inst->seqNum <
753 loadQueue[stallingLoadIdx]->seqNum)) {
754 stalled = true;
755 stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
756 stallingLoadIdx = load_idx;
757 }
758
759 // Tell IQ/mem dep unit that this instruction will need to be
760 // rescheduled eventually
761 iewStage->rescheduleMemInst(load_inst);
762 iewStage->decrWb(load_inst->seqNum);
763 load_inst->clearIssued();
764 ++lsqRescheduledLoads;
765
766 // Do not generate a writeback event as this instruction is not
767 // complete.
768 DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
769 "Store idx %i to load addr %#x\n",
770 store_idx, req->getVaddr());
771
772 // Must delete request now that it wasn't handed off to
773 // memory. This is quite ugly. @todo: Figure out the
774 // proper place to really handle request deletes.
775 delete req;
776 if (TheISA::HasUnalignedMemAcc && sreqLow) {
777 delete sreqLow;
778 delete sreqHigh;
779 }
780
781 return NoFault;
782 }
783 }
784
785 // If there's no forwarding case, then go access memory
786 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %s\n",
787 load_inst->seqNum, load_inst->pcState());
788
789 assert(!load_inst->memData);
|
780 load_inst->memData = new uint8_t[64];
| 790 load_inst->memData = new uint8_t[req->getSize()];
|
781
782 ++usedPorts;
783
784 // if we the cache is not blocked, do cache access
785 bool completedFirst = false;
786 if (!lsq->cacheBlocked()) {
787 MemCmd command =
788 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq;
789 PacketPtr data_pkt = new Packet(req, command);
790 PacketPtr fst_data_pkt = NULL;
791 PacketPtr snd_data_pkt = NULL;
792
793 data_pkt->dataStatic(load_inst->memData);
794
795 LSQSenderState *state = new LSQSenderState;
796 state->isLoad = true;
797 state->idx = load_idx;
798 state->inst = load_inst;
799 data_pkt->senderState = state;
800
801 if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
802
803 // Point the first packet at the main data packet.
804 fst_data_pkt = data_pkt;
805 } else {
806
807 // Create the split packets.
808 fst_data_pkt = new Packet(sreqLow, command);
809 snd_data_pkt = new Packet(sreqHigh, command);
810
811 fst_data_pkt->dataStatic(load_inst->memData);
812 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
813
814 fst_data_pkt->senderState = state;
815 snd_data_pkt->senderState = state;
816
817 state->isSplit = true;
818 state->outstanding = 2;
819 state->mainPkt = data_pkt;
820 }
821
822 if (!dcachePort->sendTimingReq(fst_data_pkt)) {
823 // Delete state and data packet because a load retry
824 // initiates a pipeline restart; it does not retry.
825 delete state;
826 delete data_pkt->req;
827 delete data_pkt;
828 if (TheISA::HasUnalignedMemAcc && sreqLow) {
829 delete fst_data_pkt->req;
830 delete fst_data_pkt;
831 delete snd_data_pkt->req;
832 delete snd_data_pkt;
833 sreqLow = NULL;
834 sreqHigh = NULL;
835 }
836
837 req = NULL;
838
839 // If the access didn't succeed, tell the LSQ by setting
840 // the retry thread id.
841 lsq->setRetryTid(lsqID);
842 } else if (TheISA::HasUnalignedMemAcc && sreqLow) {
843 completedFirst = true;
844
845 // The first packet was sent without problems, so send this one
846 // too. If there is a problem with this packet then the whole
847 // load will be squashed, so indicate this to the state object.
848 // The first packet will return in completeDataAccess and be
849 // handled there.
850 ++usedPorts;
851 if (!dcachePort->sendTimingReq(snd_data_pkt)) {
852
853 // The main packet will be deleted in completeDataAccess.
854 delete snd_data_pkt->req;
855 delete snd_data_pkt;
856
857 state->complete();
858
859 req = NULL;
860 sreqHigh = NULL;
861
862 lsq->setRetryTid(lsqID);
863 }
864 }
865 }
866
867 // If the cache was blocked, or has become blocked due to the access,
868 // handle it.
869 if (lsq->cacheBlocked()) {
870 if (req)
871 delete req;
872 if (TheISA::HasUnalignedMemAcc && sreqLow && !completedFirst) {
873 delete sreqLow;
874 delete sreqHigh;
875 }
876
877 ++lsqCacheBlocked;
878
879 // If the first part of a split access succeeds, then let the LSQ
880 // handle the decrWb when completeDataAccess is called upon return
881 // of the requested first part of data
882 if (!completedFirst)
883 iewStage->decrWb(load_inst->seqNum);
884
885 // There's an older load that's already going to squash.
886 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
887 return NoFault;
888
889 // Record that the load was blocked due to memory. This
890 // load will squash all instructions after it, be
891 // refetched, and re-executed.
892 isLoadBlocked = true;
893 loadBlockedHandled = false;
894 blockedLoadSeqNum = load_inst->seqNum;
895 // No fault occurred, even though the interface is blocked.
896 return NoFault;
897 }
898
899 return NoFault;
900}
901
902template <class Impl>
903Fault
904LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh,
905 uint8_t *data, int store_idx)
906{
907 assert(storeQueue[store_idx].inst);
908
909 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x"
910 " | storeHead:%i [sn:%i]\n",
911 store_idx, req->getPaddr(), data, storeHead,
912 storeQueue[store_idx].inst->seqNum);
913
914 storeQueue[store_idx].req = req;
915 storeQueue[store_idx].sreqLow = sreqLow;
916 storeQueue[store_idx].sreqHigh = sreqHigh;
917 unsigned size = req->getSize();
918 storeQueue[store_idx].size = size;
| 791
792 ++usedPorts;
793
794 // if we the cache is not blocked, do cache access
795 bool completedFirst = false;
796 if (!lsq->cacheBlocked()) {
797 MemCmd command =
798 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq;
799 PacketPtr data_pkt = new Packet(req, command);
800 PacketPtr fst_data_pkt = NULL;
801 PacketPtr snd_data_pkt = NULL;
802
803 data_pkt->dataStatic(load_inst->memData);
804
805 LSQSenderState *state = new LSQSenderState;
806 state->isLoad = true;
807 state->idx = load_idx;
808 state->inst = load_inst;
809 data_pkt->senderState = state;
810
811 if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
812
813 // Point the first packet at the main data packet.
814 fst_data_pkt = data_pkt;
815 } else {
816
817 // Create the split packets.
818 fst_data_pkt = new Packet(sreqLow, command);
819 snd_data_pkt = new Packet(sreqHigh, command);
820
821 fst_data_pkt->dataStatic(load_inst->memData);
822 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
823
824 fst_data_pkt->senderState = state;
825 snd_data_pkt->senderState = state;
826
827 state->isSplit = true;
828 state->outstanding = 2;
829 state->mainPkt = data_pkt;
830 }
831
832 if (!dcachePort->sendTimingReq(fst_data_pkt)) {
833 // Delete state and data packet because a load retry
834 // initiates a pipeline restart; it does not retry.
835 delete state;
836 delete data_pkt->req;
837 delete data_pkt;
838 if (TheISA::HasUnalignedMemAcc && sreqLow) {
839 delete fst_data_pkt->req;
840 delete fst_data_pkt;
841 delete snd_data_pkt->req;
842 delete snd_data_pkt;
843 sreqLow = NULL;
844 sreqHigh = NULL;
845 }
846
847 req = NULL;
848
849 // If the access didn't succeed, tell the LSQ by setting
850 // the retry thread id.
851 lsq->setRetryTid(lsqID);
852 } else if (TheISA::HasUnalignedMemAcc && sreqLow) {
853 completedFirst = true;
854
855 // The first packet was sent without problems, so send this one
856 // too. If there is a problem with this packet then the whole
857 // load will be squashed, so indicate this to the state object.
858 // The first packet will return in completeDataAccess and be
859 // handled there.
860 ++usedPorts;
861 if (!dcachePort->sendTimingReq(snd_data_pkt)) {
862
863 // The main packet will be deleted in completeDataAccess.
864 delete snd_data_pkt->req;
865 delete snd_data_pkt;
866
867 state->complete();
868
869 req = NULL;
870 sreqHigh = NULL;
871
872 lsq->setRetryTid(lsqID);
873 }
874 }
875 }
876
877 // If the cache was blocked, or has become blocked due to the access,
878 // handle it.
879 if (lsq->cacheBlocked()) {
880 if (req)
881 delete req;
882 if (TheISA::HasUnalignedMemAcc && sreqLow && !completedFirst) {
883 delete sreqLow;
884 delete sreqHigh;
885 }
886
887 ++lsqCacheBlocked;
888
889 // If the first part of a split access succeeds, then let the LSQ
890 // handle the decrWb when completeDataAccess is called upon return
891 // of the requested first part of data
892 if (!completedFirst)
893 iewStage->decrWb(load_inst->seqNum);
894
895 // There's an older load that's already going to squash.
896 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
897 return NoFault;
898
899 // Record that the load was blocked due to memory. This
900 // load will squash all instructions after it, be
901 // refetched, and re-executed.
902 isLoadBlocked = true;
903 loadBlockedHandled = false;
904 blockedLoadSeqNum = load_inst->seqNum;
905 // No fault occurred, even though the interface is blocked.
906 return NoFault;
907 }
908
909 return NoFault;
910}
911
912template <class Impl>
913Fault
914LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh,
915 uint8_t *data, int store_idx)
916{
917 assert(storeQueue[store_idx].inst);
918
919 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x"
920 " | storeHead:%i [sn:%i]\n",
921 store_idx, req->getPaddr(), data, storeHead,
922 storeQueue[store_idx].inst->seqNum);
923
924 storeQueue[store_idx].req = req;
925 storeQueue[store_idx].sreqLow = sreqLow;
926 storeQueue[store_idx].sreqHigh = sreqHigh;
927 unsigned size = req->getSize();
928 storeQueue[store_idx].size = size;
|
919 assert(size <= sizeof(storeQueue[store_idx].data));
| 929 storeQueue[store_idx].isAllZeros = req->getFlags() & Request::CACHE_BLOCK_ZERO;
930 assert(size <= sizeof(storeQueue[store_idx].data) ||
931 (req->getFlags() & Request::CACHE_BLOCK_ZERO));
|
920
921 // Split stores can only occur in ISAs with unaligned memory accesses. If
922 // a store request has been split, sreqLow and sreqHigh will be non-null.
923 if (TheISA::HasUnalignedMemAcc && sreqLow) {
924 storeQueue[store_idx].isSplit = true;
925 }
926
| 932
933 // Split stores can only occur in ISAs with unaligned memory accesses. If
934 // a store request has been split, sreqLow and sreqHigh will be non-null.
935 if (TheISA::HasUnalignedMemAcc && sreqLow) {
936 storeQueue[store_idx].isSplit = true;
937 }
938
|
927 memcpy(storeQueue[store_idx].data, data, size);
| 939 if (!(req->getFlags() & Request::CACHE_BLOCK_ZERO))
940 memcpy(storeQueue[store_idx].data, data, size);
|
928
929 // This function only writes the data to the store queue, so no fault
930 // can happen here.
931 return NoFault;
932}
933
934#endif // __CPU_O3_LSQ_UNIT_HH__
| 941
942 // This function only writes the data to the store queue, so no fault
943 // can happen here.
944 return NoFault;
945}
946
947#endif // __CPU_O3_LSQ_UNIT_HH__
|