1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_LSQ_UNIT_HH__ 33#define __CPU_O3_LSQ_UNIT_HH__ 34 35#include <algorithm> 36#include <cstring> 37#include <map> 38#include <queue> 39 40#include "arch/generic/debugfaults.hh" 41#include "arch/isa_traits.hh" 42#include "arch/locked_mem.hh" 43#include "arch/mmapped_ipr.hh" 44#include "base/hashmap.hh" 45#include "config/the_isa.hh" 46#include "cpu/inst_seq.hh" 47#include "cpu/timebuf.hh" 48#include "debug/LSQUnit.hh" 49#include "mem/packet.hh" 50#include "mem/port.hh" 51#include "sim/fault_fwd.hh" 52 53struct DerivO3CPUParams; 54 55/** 56 * Class that implements the actual LQ and SQ for each specific 57 * thread. Both are circular queues; load entries are freed upon 58 * committing, while store entries are freed once they writeback. The 59 * LSQUnit tracks if there are memory ordering violations, and also 60 * detects partial load to store forwarding cases (a store only has 61 * part of a load's data) that requires the load to wait until the 62 * store writes back. In the former case it holds onto the instruction 63 * until the dependence unit looks at it, and in the latter it stalls 64 * the LSQ until the store writes back. At that point the load is 65 * replayed. 66 */ 67template <class Impl> 68class LSQUnit { 69 public: 70 typedef typename Impl::O3CPU O3CPU; 71 typedef typename Impl::DynInstPtr DynInstPtr; 72 typedef typename Impl::CPUPol::IEW IEW; 73 typedef typename Impl::CPUPol::LSQ LSQ; 74 typedef typename Impl::CPUPol::IssueStruct IssueStruct; 75 76 public: 77 /** Constructs an LSQ unit. init() must be called prior to use. */ 78 LSQUnit(); 79 80 /** Initializes the LSQ unit with the specified number of entries. */ 81 void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 82 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 83 unsigned id); 84 85 /** Returns the name of the LSQ unit. */ 86 std::string name() const; 87 88 /** Registers statistics. */ 89 void regStats(); 90 91 /** Sets the pointer to the dcache port. */ 92 void setDcachePort(MasterPort *dcache_port); 93 94 /** Switches out LSQ unit. */ 95 void switchOut(); 96 97 /** Takes over from another CPU's thread. */ 98 void takeOverFrom(); 99 100 /** Returns if the LSQ is switched out. */ 101 bool isSwitchedOut() { return switchedOut; } 102 103 /** Ticks the LSQ unit, which in this case only resets the number of 104 * used cache ports. 105 * @todo: Move the number of used ports up to the LSQ level so it can 106 * be shared by all LSQ units. 107 */ 108 void tick() { usedPorts = 0; } 109 110 /** Inserts an instruction. */ 111 void insert(DynInstPtr &inst); 112 /** Inserts a load instruction. */ 113 void insertLoad(DynInstPtr &load_inst); 114 /** Inserts a store instruction. */ 115 void insertStore(DynInstPtr &store_inst); 116 117 /** Check for ordering violations in the LSQ. For a store squash if we 118 * ever find a conflicting load. For a load, only squash if we 119 * an external snoop invalidate has been seen for that load address 120 * @param load_idx index to start checking at 121 * @param inst the instruction to check 122 */ 123 Fault checkViolations(int load_idx, DynInstPtr &inst); 124 125 /** Check if an incoming invalidate hits in the lsq on a load 126 * that might have issued out of order wrt another load beacuse 127 * of the intermediate invalidate. 128 */ 129 void checkSnoop(PacketPtr pkt); 130 131 /** Executes a load instruction. */ 132 Fault executeLoad(DynInstPtr &inst); 133 134 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; } 135 /** Executes a store instruction. */ 136 Fault executeStore(DynInstPtr &inst); 137 138 /** Commits the head load. */ 139 void commitLoad(); 140 /** Commits loads older than a specific sequence number. */ 141 void commitLoads(InstSeqNum &youngest_inst); 142 143 /** Commits stores older than a specific sequence number. */ 144 void commitStores(InstSeqNum &youngest_inst); 145 146 /** Writes back stores. */ 147 void writebackStores(); 148 149 /** Completes the data access that has been returned from the 150 * memory system. */ 151 void completeDataAccess(PacketPtr pkt); 152 153 /** Clears all the entries in the LQ. */ 154 void clearLQ(); 155 156 /** Clears all the entries in the SQ. */ 157 void clearSQ(); 158 159 /** Resizes the LQ to a given size. */ 160 void resizeLQ(unsigned size); 161 162 /** Resizes the SQ to a given size. */ 163 void resizeSQ(unsigned size); 164 165 /** Squashes all instructions younger than a specific sequence number. */ 166 void squash(const InstSeqNum &squashed_num); 167 168 /** Returns if there is a memory ordering violation. Value is reset upon 169 * call to getMemDepViolator(). 170 */ 171 bool violation() { return memDepViolator; } 172 173 /** Returns the memory ordering violator. */ 174 DynInstPtr getMemDepViolator(); 175 176 /** Returns if a load became blocked due to the memory system. */ 177 bool loadBlocked() 178 { return isLoadBlocked; } 179 180 /** Clears the signal that a load became blocked. */ 181 void clearLoadBlocked() 182 { isLoadBlocked = false; } 183 184 /** Returns if the blocked load was handled. */ 185 bool isLoadBlockedHandled() 186 { return loadBlockedHandled; } 187 188 /** Records the blocked load as being handled. */ 189 void setLoadBlockedHandled() 190 { loadBlockedHandled = true; } 191 192 /** Returns the number of free entries (min of free LQ and SQ entries). */ 193 unsigned numFreeEntries(); 194 195 /** Returns the number of loads ready to execute. */ 196 int numLoadsReady(); 197 198 /** Returns the number of loads in the LQ. */ 199 int numLoads() { return loads; } 200 201 /** Returns the number of stores in the SQ. */ 202 int numStores() { return stores; } 203 204 /** Returns if either the LQ or SQ is full. */ 205 bool isFull() { return lqFull() || sqFull(); } 206 207 /** Returns if the LQ is full. */ 208 bool lqFull() { return loads >= (LQEntries - 1); } 209 210 /** Returns if the SQ is full. */ 211 bool sqFull() { return stores >= (SQEntries - 1); } 212 213 /** Returns the number of instructions in the LSQ. */ 214 unsigned getCount() { return loads + stores; } 215 216 /** Returns if there are any stores to writeback. */ 217 bool hasStoresToWB() { return storesToWB; } 218 219 /** Returns the number of stores to writeback. */ 220 int numStoresToWB() { return storesToWB; } 221 222 /** Returns if the LSQ unit will writeback on this cycle. */ 223 bool willWB() { return storeQueue[storeWBIdx].canWB && 224 !storeQueue[storeWBIdx].completed && 225 !isStoreBlocked; } 226 227 /** Handles doing the retry. */ 228 void recvRetry(); 229 230 private: 231 /** Writes back the instruction, sending it to IEW. */ 232 void writeback(DynInstPtr &inst, PacketPtr pkt); 233 234 /** Writes back a store that couldn't be completed the previous cycle. */ 235 void writebackPendingStore(); 236 237 /** Handles completing the send of a store to memory. */ 238 void storePostSend(PacketPtr pkt); 239 240 /** Completes the store at the specified index. */ 241 void completeStore(int store_idx); 242 243 /** Attempts to send a store to the cache. */ 244 bool sendStore(PacketPtr data_pkt); 245 246 /** Increments the given store index (circular queue). */ 247 inline void incrStIdx(int &store_idx); 248 /** Decrements the given store index (circular queue). */ 249 inline void decrStIdx(int &store_idx); 250 /** Increments the given load index (circular queue). */ 251 inline void incrLdIdx(int &load_idx); 252 /** Decrements the given load index (circular queue). */ 253 inline void decrLdIdx(int &load_idx); 254 255 public: 256 /** Debugging function to dump instructions in the LSQ. */ 257 void dumpInsts(); 258 259 private: 260 /** Pointer to the CPU. */ 261 O3CPU *cpu; 262 263 /** Pointer to the IEW stage. */ 264 IEW *iewStage; 265 266 /** Pointer to the LSQ. */ 267 LSQ *lsq; 268 269 /** Pointer to the dcache port. Used only for sending. */ 270 MasterPort *dcachePort; 271 272 /** Derived class to hold any sender state the LSQ needs. */ 273 class LSQSenderState : public Packet::SenderState 274 { 275 public: 276 /** Default constructor. */ 277 LSQSenderState()
| 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_LSQ_UNIT_HH__ 33#define __CPU_O3_LSQ_UNIT_HH__ 34 35#include <algorithm> 36#include <cstring> 37#include <map> 38#include <queue> 39 40#include "arch/generic/debugfaults.hh" 41#include "arch/isa_traits.hh" 42#include "arch/locked_mem.hh" 43#include "arch/mmapped_ipr.hh" 44#include "base/hashmap.hh" 45#include "config/the_isa.hh" 46#include "cpu/inst_seq.hh" 47#include "cpu/timebuf.hh" 48#include "debug/LSQUnit.hh" 49#include "mem/packet.hh" 50#include "mem/port.hh" 51#include "sim/fault_fwd.hh" 52 53struct DerivO3CPUParams; 54 55/** 56 * Class that implements the actual LQ and SQ for each specific 57 * thread. Both are circular queues; load entries are freed upon 58 * committing, while store entries are freed once they writeback. The 59 * LSQUnit tracks if there are memory ordering violations, and also 60 * detects partial load to store forwarding cases (a store only has 61 * part of a load's data) that requires the load to wait until the 62 * store writes back. In the former case it holds onto the instruction 63 * until the dependence unit looks at it, and in the latter it stalls 64 * the LSQ until the store writes back. At that point the load is 65 * replayed. 66 */ 67template <class Impl> 68class LSQUnit { 69 public: 70 typedef typename Impl::O3CPU O3CPU; 71 typedef typename Impl::DynInstPtr DynInstPtr; 72 typedef typename Impl::CPUPol::IEW IEW; 73 typedef typename Impl::CPUPol::LSQ LSQ; 74 typedef typename Impl::CPUPol::IssueStruct IssueStruct; 75 76 public: 77 /** Constructs an LSQ unit. init() must be called prior to use. */ 78 LSQUnit(); 79 80 /** Initializes the LSQ unit with the specified number of entries. */ 81 void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 82 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 83 unsigned id); 84 85 /** Returns the name of the LSQ unit. */ 86 std::string name() const; 87 88 /** Registers statistics. */ 89 void regStats(); 90 91 /** Sets the pointer to the dcache port. */ 92 void setDcachePort(MasterPort *dcache_port); 93 94 /** Switches out LSQ unit. */ 95 void switchOut(); 96 97 /** Takes over from another CPU's thread. */ 98 void takeOverFrom(); 99 100 /** Returns if the LSQ is switched out. */ 101 bool isSwitchedOut() { return switchedOut; } 102 103 /** Ticks the LSQ unit, which in this case only resets the number of 104 * used cache ports. 105 * @todo: Move the number of used ports up to the LSQ level so it can 106 * be shared by all LSQ units. 107 */ 108 void tick() { usedPorts = 0; } 109 110 /** Inserts an instruction. */ 111 void insert(DynInstPtr &inst); 112 /** Inserts a load instruction. */ 113 void insertLoad(DynInstPtr &load_inst); 114 /** Inserts a store instruction. */ 115 void insertStore(DynInstPtr &store_inst); 116 117 /** Check for ordering violations in the LSQ. For a store squash if we 118 * ever find a conflicting load. For a load, only squash if we 119 * an external snoop invalidate has been seen for that load address 120 * @param load_idx index to start checking at 121 * @param inst the instruction to check 122 */ 123 Fault checkViolations(int load_idx, DynInstPtr &inst); 124 125 /** Check if an incoming invalidate hits in the lsq on a load 126 * that might have issued out of order wrt another load beacuse 127 * of the intermediate invalidate. 128 */ 129 void checkSnoop(PacketPtr pkt); 130 131 /** Executes a load instruction. */ 132 Fault executeLoad(DynInstPtr &inst); 133 134 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; } 135 /** Executes a store instruction. */ 136 Fault executeStore(DynInstPtr &inst); 137 138 /** Commits the head load. */ 139 void commitLoad(); 140 /** Commits loads older than a specific sequence number. */ 141 void commitLoads(InstSeqNum &youngest_inst); 142 143 /** Commits stores older than a specific sequence number. */ 144 void commitStores(InstSeqNum &youngest_inst); 145 146 /** Writes back stores. */ 147 void writebackStores(); 148 149 /** Completes the data access that has been returned from the 150 * memory system. */ 151 void completeDataAccess(PacketPtr pkt); 152 153 /** Clears all the entries in the LQ. */ 154 void clearLQ(); 155 156 /** Clears all the entries in the SQ. */ 157 void clearSQ(); 158 159 /** Resizes the LQ to a given size. */ 160 void resizeLQ(unsigned size); 161 162 /** Resizes the SQ to a given size. */ 163 void resizeSQ(unsigned size); 164 165 /** Squashes all instructions younger than a specific sequence number. */ 166 void squash(const InstSeqNum &squashed_num); 167 168 /** Returns if there is a memory ordering violation. Value is reset upon 169 * call to getMemDepViolator(). 170 */ 171 bool violation() { return memDepViolator; } 172 173 /** Returns the memory ordering violator. */ 174 DynInstPtr getMemDepViolator(); 175 176 /** Returns if a load became blocked due to the memory system. */ 177 bool loadBlocked() 178 { return isLoadBlocked; } 179 180 /** Clears the signal that a load became blocked. */ 181 void clearLoadBlocked() 182 { isLoadBlocked = false; } 183 184 /** Returns if the blocked load was handled. */ 185 bool isLoadBlockedHandled() 186 { return loadBlockedHandled; } 187 188 /** Records the blocked load as being handled. */ 189 void setLoadBlockedHandled() 190 { loadBlockedHandled = true; } 191 192 /** Returns the number of free entries (min of free LQ and SQ entries). */ 193 unsigned numFreeEntries(); 194 195 /** Returns the number of loads ready to execute. */ 196 int numLoadsReady(); 197 198 /** Returns the number of loads in the LQ. */ 199 int numLoads() { return loads; } 200 201 /** Returns the number of stores in the SQ. */ 202 int numStores() { return stores; } 203 204 /** Returns if either the LQ or SQ is full. */ 205 bool isFull() { return lqFull() || sqFull(); } 206 207 /** Returns if the LQ is full. */ 208 bool lqFull() { return loads >= (LQEntries - 1); } 209 210 /** Returns if the SQ is full. */ 211 bool sqFull() { return stores >= (SQEntries - 1); } 212 213 /** Returns the number of instructions in the LSQ. */ 214 unsigned getCount() { return loads + stores; } 215 216 /** Returns if there are any stores to writeback. */ 217 bool hasStoresToWB() { return storesToWB; } 218 219 /** Returns the number of stores to writeback. */ 220 int numStoresToWB() { return storesToWB; } 221 222 /** Returns if the LSQ unit will writeback on this cycle. */ 223 bool willWB() { return storeQueue[storeWBIdx].canWB && 224 !storeQueue[storeWBIdx].completed && 225 !isStoreBlocked; } 226 227 /** Handles doing the retry. */ 228 void recvRetry(); 229 230 private: 231 /** Writes back the instruction, sending it to IEW. */ 232 void writeback(DynInstPtr &inst, PacketPtr pkt); 233 234 /** Writes back a store that couldn't be completed the previous cycle. */ 235 void writebackPendingStore(); 236 237 /** Handles completing the send of a store to memory. */ 238 void storePostSend(PacketPtr pkt); 239 240 /** Completes the store at the specified index. */ 241 void completeStore(int store_idx); 242 243 /** Attempts to send a store to the cache. */ 244 bool sendStore(PacketPtr data_pkt); 245 246 /** Increments the given store index (circular queue). */ 247 inline void incrStIdx(int &store_idx); 248 /** Decrements the given store index (circular queue). */ 249 inline void decrStIdx(int &store_idx); 250 /** Increments the given load index (circular queue). */ 251 inline void incrLdIdx(int &load_idx); 252 /** Decrements the given load index (circular queue). */ 253 inline void decrLdIdx(int &load_idx); 254 255 public: 256 /** Debugging function to dump instructions in the LSQ. */ 257 void dumpInsts(); 258 259 private: 260 /** Pointer to the CPU. */ 261 O3CPU *cpu; 262 263 /** Pointer to the IEW stage. */ 264 IEW *iewStage; 265 266 /** Pointer to the LSQ. */ 267 LSQ *lsq; 268 269 /** Pointer to the dcache port. Used only for sending. */ 270 MasterPort *dcachePort; 271 272 /** Derived class to hold any sender state the LSQ needs. */ 273 class LSQSenderState : public Packet::SenderState 274 { 275 public: 276 /** Default constructor. */ 277 LSQSenderState()
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278 : noWB(false), isSplit(false), pktToSend(false), outstanding(1), 279 mainPkt(NULL), pendingPacket(NULL) 280 { }
| 278 : mainPkt(NULL), pendingPacket(NULL), outstanding(1), 279 noWB(false), isSplit(false), pktToSend(false) 280 { }
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281 282 /** Instruction who initiated the access to memory. */ 283 DynInstPtr inst;
| 281 282 /** Instruction who initiated the access to memory. */ 283 DynInstPtr inst;
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| 284 /** The main packet from a split load, used during writeback. */ 285 PacketPtr mainPkt; 286 /** A second packet from a split store that needs sending. */ 287 PacketPtr pendingPacket; 288 /** The LQ/SQ index of the instruction. */ 289 uint8_t idx; 290 /** Number of outstanding packets to complete. */ 291 uint8_t outstanding;
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284 /** Whether or not it is a load. */ 285 bool isLoad;
| 292 /** Whether or not it is a load. */ 293 bool isLoad;
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286 /** The LQ/SQ index of the instruction. */ 287 int idx;
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288 /** Whether or not the instruction will need to writeback. */ 289 bool noWB; 290 /** Whether or not this access is split in two. */ 291 bool isSplit; 292 /** Whether or not there is a packet that needs sending. */ 293 bool pktToSend;
| 294 /** Whether or not the instruction will need to writeback. */ 295 bool noWB; 296 /** Whether or not this access is split in two. */ 297 bool isSplit; 298 /** Whether or not there is a packet that needs sending. */ 299 bool pktToSend;
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294 /** Number of outstanding packets to complete. */ 295 int outstanding; 296 /** The main packet from a split load, used during writeback. */ 297 PacketPtr mainPkt; 298 /** A second packet from a split store that needs sending. */ 299 PacketPtr pendingPacket;
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300 301 /** Completes a packet and returns whether the access is finished. */ 302 inline bool complete() { return --outstanding == 0; } 303 }; 304 305 /** Writeback event, specifically for when stores forward data to loads. */ 306 class WritebackEvent : public Event { 307 public: 308 /** Constructs a writeback event. */ 309 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr); 310 311 /** Processes the writeback event. */ 312 void process(); 313 314 /** Returns the description of this event. */ 315 const char *description() const; 316 317 private: 318 /** Instruction whose results are being written back. */ 319 DynInstPtr inst; 320 321 /** The packet that would have been sent to memory. */ 322 PacketPtr pkt; 323 324 /** The pointer to the LSQ unit that issued the store. */ 325 LSQUnit<Impl> *lsqPtr; 326 }; 327 328 public: 329 struct SQEntry { 330 /** Constructs an empty store queue entry. */ 331 SQEntry() 332 : inst(NULL), req(NULL), size(0), 333 canWB(0), committed(0), completed(0) 334 { 335 std::memset(data, 0, sizeof(data)); 336 } 337 338 /** Constructs a store queue entry for a given instruction. */ 339 SQEntry(DynInstPtr &_inst) 340 : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0), 341 isSplit(0), canWB(0), committed(0), completed(0) 342 { 343 std::memset(data, 0, sizeof(data)); 344 }
| 300 301 /** Completes a packet and returns whether the access is finished. */ 302 inline bool complete() { return --outstanding == 0; } 303 }; 304 305 /** Writeback event, specifically for when stores forward data to loads. */ 306 class WritebackEvent : public Event { 307 public: 308 /** Constructs a writeback event. */ 309 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr); 310 311 /** Processes the writeback event. */ 312 void process(); 313 314 /** Returns the description of this event. */ 315 const char *description() const; 316 317 private: 318 /** Instruction whose results are being written back. */ 319 DynInstPtr inst; 320 321 /** The packet that would have been sent to memory. */ 322 PacketPtr pkt; 323 324 /** The pointer to the LSQ unit that issued the store. */ 325 LSQUnit<Impl> *lsqPtr; 326 }; 327 328 public: 329 struct SQEntry { 330 /** Constructs an empty store queue entry. */ 331 SQEntry() 332 : inst(NULL), req(NULL), size(0), 333 canWB(0), committed(0), completed(0) 334 { 335 std::memset(data, 0, sizeof(data)); 336 } 337 338 /** Constructs a store queue entry for a given instruction. */ 339 SQEntry(DynInstPtr &_inst) 340 : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0), 341 isSplit(0), canWB(0), committed(0), completed(0) 342 { 343 std::memset(data, 0, sizeof(data)); 344 }
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345
| 345 /** The store data. */ 346 char data[16];
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346 /** The store instruction. */ 347 DynInstPtr inst; 348 /** The request for the store. */ 349 RequestPtr req; 350 /** The split requests for the store. */ 351 RequestPtr sreqLow; 352 RequestPtr sreqHigh; 353 /** The size of the store. */
| 347 /** The store instruction. */ 348 DynInstPtr inst; 349 /** The request for the store. */ 350 RequestPtr req; 351 /** The split requests for the store. */ 352 RequestPtr sreqLow; 353 RequestPtr sreqHigh; 354 /** The size of the store. */
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354 int size; 355 /** The store data. */ 356 char data[16];
| 355 uint8_t size;
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357 /** Whether or not the store is split into two requests. */ 358 bool isSplit; 359 /** Whether or not the store can writeback. */ 360 bool canWB; 361 /** Whether or not the store is committed. */ 362 bool committed; 363 /** Whether or not the store is completed. */ 364 bool completed; 365 }; 366 367 private: 368 /** The LSQUnit thread id. */ 369 ThreadID lsqID; 370 371 /** The store queue. */ 372 std::vector<SQEntry> storeQueue; 373 374 /** The load queue. */ 375 std::vector<DynInstPtr> loadQueue; 376 377 /** The number of LQ entries, plus a sentinel entry (circular queue). 378 * @todo: Consider having var that records the true number of LQ entries. 379 */ 380 unsigned LQEntries; 381 /** The number of SQ entries, plus a sentinel entry (circular queue). 382 * @todo: Consider having var that records the true number of SQ entries. 383 */ 384 unsigned SQEntries; 385 386 /** The number of places to shift addresses in the LSQ before checking 387 * for dependency violations 388 */ 389 unsigned depCheckShift; 390 391 /** Should loads be checked for dependency issues */ 392 bool checkLoads; 393 394 /** The number of load instructions in the LQ. */ 395 int loads; 396 /** The number of store instructions in the SQ. */ 397 int stores; 398 /** The number of store instructions in the SQ waiting to writeback. */ 399 int storesToWB; 400 401 /** The index of the head instruction in the LQ. */ 402 int loadHead; 403 /** The index of the tail instruction in the LQ. */ 404 int loadTail; 405 406 /** The index of the head instruction in the SQ. */ 407 int storeHead; 408 /** The index of the first instruction that may be ready to be 409 * written back, and has not yet been written back. 410 */ 411 int storeWBIdx; 412 /** The index of the tail instruction in the SQ. */ 413 int storeTail; 414 415 /// @todo Consider moving to a more advanced model with write vs read ports 416 /** The number of cache ports available each cycle. */ 417 int cachePorts; 418 419 /** The number of used cache ports in this cycle. */ 420 int usedPorts; 421 422 /** Is the LSQ switched out. */ 423 bool switchedOut; 424 425 //list<InstSeqNum> mshrSeqNums; 426 427 /** Address Mask for a cache block (e.g. ~(cache_block_size-1)) */ 428 Addr cacheBlockMask; 429 430 /** Wire to read information from the issue stage time queue. */ 431 typename TimeBuffer<IssueStruct>::wire fromIssue; 432 433 /** Whether or not the LSQ is stalled. */ 434 bool stalled; 435 /** The store that causes the stall due to partial store to load 436 * forwarding. 437 */ 438 InstSeqNum stallingStoreIsn; 439 /** The index of the above store. */ 440 int stallingLoadIdx; 441 442 /** The packet that needs to be retried. */ 443 PacketPtr retryPkt; 444 445 /** Whehter or not a store is blocked due to the memory system. */ 446 bool isStoreBlocked; 447 448 /** Whether or not a load is blocked due to the memory system. */ 449 bool isLoadBlocked; 450 451 /** Has the blocked load been handled. */ 452 bool loadBlockedHandled; 453 454 /** Whether or not a store is in flight. */ 455 bool storeInFlight; 456 457 /** The sequence number of the blocked load. */ 458 InstSeqNum blockedLoadSeqNum; 459 460 /** The oldest load that caused a memory ordering violation. */ 461 DynInstPtr memDepViolator; 462 463 /** Whether or not there is a packet that couldn't be sent because of 464 * a lack of cache ports. */ 465 bool hasPendingPkt; 466 467 /** The packet that is pending free cache ports. */ 468 PacketPtr pendingPkt; 469 470 /** Flag for memory model. */ 471 bool needsTSO; 472 473 // Will also need how many read/write ports the Dcache has. Or keep track 474 // of that in stage that is one level up, and only call executeLoad/Store 475 // the appropriate number of times. 476 /** Total number of loads forwaded from LSQ stores. */ 477 Stats::Scalar lsqForwLoads; 478 479 /** Total number of loads ignored due to invalid addresses. */ 480 Stats::Scalar invAddrLoads; 481 482 /** Total number of squashed loads. */ 483 Stats::Scalar lsqSquashedLoads; 484 485 /** Total number of responses from the memory system that are 486 * ignored due to the instruction already being squashed. */ 487 Stats::Scalar lsqIgnoredResponses; 488 489 /** Tota number of memory ordering violations. */ 490 Stats::Scalar lsqMemOrderViolation; 491 492 /** Total number of squashed stores. */ 493 Stats::Scalar lsqSquashedStores; 494 495 /** Total number of software prefetches ignored due to invalid addresses. */ 496 Stats::Scalar invAddrSwpfs; 497 498 /** Ready loads blocked due to partial store-forwarding. */ 499 Stats::Scalar lsqBlockedLoads; 500 501 /** Number of loads that were rescheduled. */ 502 Stats::Scalar lsqRescheduledLoads; 503 504 /** Number of times the LSQ is blocked due to the cache. */ 505 Stats::Scalar lsqCacheBlocked; 506 507 public: 508 /** Executes the load at the given index. */ 509 Fault read(Request *req, Request *sreqLow, Request *sreqHigh, 510 uint8_t *data, int load_idx); 511 512 /** Executes the store at the given index. */ 513 Fault write(Request *req, Request *sreqLow, Request *sreqHigh, 514 uint8_t *data, int store_idx); 515 516 /** Returns the index of the head load instruction. */ 517 int getLoadHead() { return loadHead; } 518 /** Returns the sequence number of the head load instruction. */ 519 InstSeqNum getLoadHeadSeqNum() 520 { 521 if (loadQueue[loadHead]) { 522 return loadQueue[loadHead]->seqNum; 523 } else { 524 return 0; 525 } 526 527 } 528 529 /** Returns the index of the head store instruction. */ 530 int getStoreHead() { return storeHead; } 531 /** Returns the sequence number of the head store instruction. */ 532 InstSeqNum getStoreHeadSeqNum() 533 { 534 if (storeQueue[storeHead].inst) { 535 return storeQueue[storeHead].inst->seqNum; 536 } else { 537 return 0; 538 } 539 540 } 541 542 /** Returns whether or not the LSQ unit is stalled. */ 543 bool isStalled() { return stalled; } 544}; 545 546template <class Impl> 547Fault 548LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, 549 uint8_t *data, int load_idx) 550{ 551 DynInstPtr load_inst = loadQueue[load_idx]; 552 553 assert(load_inst); 554 555 assert(!load_inst->isExecuted()); 556 557 // Make sure this isn't an uncacheable access 558 // A bit of a hackish way to get uncached accesses to work only if they're 559 // at the head of the LSQ and are ready to commit (at the head of the ROB 560 // too). 561 if (req->isUncacheable() && 562 (load_idx != loadHead || !load_inst->isAtCommit())) { 563 iewStage->rescheduleMemInst(load_inst); 564 ++lsqRescheduledLoads; 565 DPRINTF(LSQUnit, "Uncachable load [sn:%lli] PC %s\n", 566 load_inst->seqNum, load_inst->pcState()); 567 568 // Must delete request now that it wasn't handed off to 569 // memory. This is quite ugly. @todo: Figure out the proper 570 // place to really handle request deletes. 571 delete req; 572 if (TheISA::HasUnalignedMemAcc && sreqLow) { 573 delete sreqLow; 574 delete sreqHigh; 575 } 576 return new GenericISA::M5PanicFault( 577 "Uncachable load [sn:%llx] PC %s\n", 578 load_inst->seqNum, load_inst->pcState()); 579 } 580 581 // Check the SQ for any previous stores that might lead to forwarding 582 int store_idx = load_inst->sqIdx; 583 584 int store_size = 0; 585 586 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, " 587 "storeHead: %i addr: %#x%s\n", 588 load_idx, store_idx, storeHead, req->getPaddr(), 589 sreqLow ? " split" : ""); 590 591 if (req->isLLSC()) { 592 assert(!sreqLow); 593 // Disable recording the result temporarily. Writing to misc 594 // regs normally updates the result, but this is not the 595 // desired behavior when handling store conditionals.
| 356 /** Whether or not the store is split into two requests. */ 357 bool isSplit; 358 /** Whether or not the store can writeback. */ 359 bool canWB; 360 /** Whether or not the store is committed. */ 361 bool committed; 362 /** Whether or not the store is completed. */ 363 bool completed; 364 }; 365 366 private: 367 /** The LSQUnit thread id. */ 368 ThreadID lsqID; 369 370 /** The store queue. */ 371 std::vector<SQEntry> storeQueue; 372 373 /** The load queue. */ 374 std::vector<DynInstPtr> loadQueue; 375 376 /** The number of LQ entries, plus a sentinel entry (circular queue). 377 * @todo: Consider having var that records the true number of LQ entries. 378 */ 379 unsigned LQEntries; 380 /** The number of SQ entries, plus a sentinel entry (circular queue). 381 * @todo: Consider having var that records the true number of SQ entries. 382 */ 383 unsigned SQEntries; 384 385 /** The number of places to shift addresses in the LSQ before checking 386 * for dependency violations 387 */ 388 unsigned depCheckShift; 389 390 /** Should loads be checked for dependency issues */ 391 bool checkLoads; 392 393 /** The number of load instructions in the LQ. */ 394 int loads; 395 /** The number of store instructions in the SQ. */ 396 int stores; 397 /** The number of store instructions in the SQ waiting to writeback. */ 398 int storesToWB; 399 400 /** The index of the head instruction in the LQ. */ 401 int loadHead; 402 /** The index of the tail instruction in the LQ. */ 403 int loadTail; 404 405 /** The index of the head instruction in the SQ. */ 406 int storeHead; 407 /** The index of the first instruction that may be ready to be 408 * written back, and has not yet been written back. 409 */ 410 int storeWBIdx; 411 /** The index of the tail instruction in the SQ. */ 412 int storeTail; 413 414 /// @todo Consider moving to a more advanced model with write vs read ports 415 /** The number of cache ports available each cycle. */ 416 int cachePorts; 417 418 /** The number of used cache ports in this cycle. */ 419 int usedPorts; 420 421 /** Is the LSQ switched out. */ 422 bool switchedOut; 423 424 //list<InstSeqNum> mshrSeqNums; 425 426 /** Address Mask for a cache block (e.g. ~(cache_block_size-1)) */ 427 Addr cacheBlockMask; 428 429 /** Wire to read information from the issue stage time queue. */ 430 typename TimeBuffer<IssueStruct>::wire fromIssue; 431 432 /** Whether or not the LSQ is stalled. */ 433 bool stalled; 434 /** The store that causes the stall due to partial store to load 435 * forwarding. 436 */ 437 InstSeqNum stallingStoreIsn; 438 /** The index of the above store. */ 439 int stallingLoadIdx; 440 441 /** The packet that needs to be retried. */ 442 PacketPtr retryPkt; 443 444 /** Whehter or not a store is blocked due to the memory system. */ 445 bool isStoreBlocked; 446 447 /** Whether or not a load is blocked due to the memory system. */ 448 bool isLoadBlocked; 449 450 /** Has the blocked load been handled. */ 451 bool loadBlockedHandled; 452 453 /** Whether or not a store is in flight. */ 454 bool storeInFlight; 455 456 /** The sequence number of the blocked load. */ 457 InstSeqNum blockedLoadSeqNum; 458 459 /** The oldest load that caused a memory ordering violation. */ 460 DynInstPtr memDepViolator; 461 462 /** Whether or not there is a packet that couldn't be sent because of 463 * a lack of cache ports. */ 464 bool hasPendingPkt; 465 466 /** The packet that is pending free cache ports. */ 467 PacketPtr pendingPkt; 468 469 /** Flag for memory model. */ 470 bool needsTSO; 471 472 // Will also need how many read/write ports the Dcache has. Or keep track 473 // of that in stage that is one level up, and only call executeLoad/Store 474 // the appropriate number of times. 475 /** Total number of loads forwaded from LSQ stores. */ 476 Stats::Scalar lsqForwLoads; 477 478 /** Total number of loads ignored due to invalid addresses. */ 479 Stats::Scalar invAddrLoads; 480 481 /** Total number of squashed loads. */ 482 Stats::Scalar lsqSquashedLoads; 483 484 /** Total number of responses from the memory system that are 485 * ignored due to the instruction already being squashed. */ 486 Stats::Scalar lsqIgnoredResponses; 487 488 /** Tota number of memory ordering violations. */ 489 Stats::Scalar lsqMemOrderViolation; 490 491 /** Total number of squashed stores. */ 492 Stats::Scalar lsqSquashedStores; 493 494 /** Total number of software prefetches ignored due to invalid addresses. */ 495 Stats::Scalar invAddrSwpfs; 496 497 /** Ready loads blocked due to partial store-forwarding. */ 498 Stats::Scalar lsqBlockedLoads; 499 500 /** Number of loads that were rescheduled. */ 501 Stats::Scalar lsqRescheduledLoads; 502 503 /** Number of times the LSQ is blocked due to the cache. */ 504 Stats::Scalar lsqCacheBlocked; 505 506 public: 507 /** Executes the load at the given index. */ 508 Fault read(Request *req, Request *sreqLow, Request *sreqHigh, 509 uint8_t *data, int load_idx); 510 511 /** Executes the store at the given index. */ 512 Fault write(Request *req, Request *sreqLow, Request *sreqHigh, 513 uint8_t *data, int store_idx); 514 515 /** Returns the index of the head load instruction. */ 516 int getLoadHead() { return loadHead; } 517 /** Returns the sequence number of the head load instruction. */ 518 InstSeqNum getLoadHeadSeqNum() 519 { 520 if (loadQueue[loadHead]) { 521 return loadQueue[loadHead]->seqNum; 522 } else { 523 return 0; 524 } 525 526 } 527 528 /** Returns the index of the head store instruction. */ 529 int getStoreHead() { return storeHead; } 530 /** Returns the sequence number of the head store instruction. */ 531 InstSeqNum getStoreHeadSeqNum() 532 { 533 if (storeQueue[storeHead].inst) { 534 return storeQueue[storeHead].inst->seqNum; 535 } else { 536 return 0; 537 } 538 539 } 540 541 /** Returns whether or not the LSQ unit is stalled. */ 542 bool isStalled() { return stalled; } 543}; 544 545template <class Impl> 546Fault 547LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, 548 uint8_t *data, int load_idx) 549{ 550 DynInstPtr load_inst = loadQueue[load_idx]; 551 552 assert(load_inst); 553 554 assert(!load_inst->isExecuted()); 555 556 // Make sure this isn't an uncacheable access 557 // A bit of a hackish way to get uncached accesses to work only if they're 558 // at the head of the LSQ and are ready to commit (at the head of the ROB 559 // too). 560 if (req->isUncacheable() && 561 (load_idx != loadHead || !load_inst->isAtCommit())) { 562 iewStage->rescheduleMemInst(load_inst); 563 ++lsqRescheduledLoads; 564 DPRINTF(LSQUnit, "Uncachable load [sn:%lli] PC %s\n", 565 load_inst->seqNum, load_inst->pcState()); 566 567 // Must delete request now that it wasn't handed off to 568 // memory. This is quite ugly. @todo: Figure out the proper 569 // place to really handle request deletes. 570 delete req; 571 if (TheISA::HasUnalignedMemAcc && sreqLow) { 572 delete sreqLow; 573 delete sreqHigh; 574 } 575 return new GenericISA::M5PanicFault( 576 "Uncachable load [sn:%llx] PC %s\n", 577 load_inst->seqNum, load_inst->pcState()); 578 } 579 580 // Check the SQ for any previous stores that might lead to forwarding 581 int store_idx = load_inst->sqIdx; 582 583 int store_size = 0; 584 585 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, " 586 "storeHead: %i addr: %#x%s\n", 587 load_idx, store_idx, storeHead, req->getPaddr(), 588 sreqLow ? " split" : ""); 589 590 if (req->isLLSC()) { 591 assert(!sreqLow); 592 // Disable recording the result temporarily. Writing to misc 593 // regs normally updates the result, but this is not the 594 // desired behavior when handling store conditionals.
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596 load_inst->recordResult = false;
| 595 load_inst->recordResult(false);
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597 TheISA::handleLockedRead(load_inst.get(), req);
| 596 TheISA::handleLockedRead(load_inst.get(), req);
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598 load_inst->recordResult = true;
| 597 load_inst->recordResult(true);
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599 } 600 601 if (req->isMmappedIpr()) { 602 assert(!load_inst->memData); 603 load_inst->memData = new uint8_t[64]; 604 605 ThreadContext *thread = cpu->tcBase(lsqID); 606 Tick delay; 607 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq); 608 609 if (!TheISA::HasUnalignedMemAcc || !sreqLow) { 610 data_pkt->dataStatic(load_inst->memData); 611 delay = TheISA::handleIprRead(thread, data_pkt); 612 } else { 613 assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr()); 614 PacketPtr fst_data_pkt = new Packet(sreqLow, MemCmd::ReadReq); 615 PacketPtr snd_data_pkt = new Packet(sreqHigh, MemCmd::ReadReq); 616 617 fst_data_pkt->dataStatic(load_inst->memData); 618 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize()); 619 620 delay = TheISA::handleIprRead(thread, fst_data_pkt); 621 unsigned delay2 = TheISA::handleIprRead(thread, snd_data_pkt); 622 if (delay2 > delay) 623 delay = delay2; 624 625 delete sreqLow; 626 delete sreqHigh; 627 delete fst_data_pkt; 628 delete snd_data_pkt; 629 } 630 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this); 631 cpu->schedule(wb, curTick() + delay); 632 return NoFault; 633 } 634 635 while (store_idx != -1) { 636 // End once we've reached the top of the LSQ 637 if (store_idx == storeWBIdx) { 638 break; 639 } 640 641 // Move the index to one younger 642 if (--store_idx < 0) 643 store_idx += SQEntries; 644 645 assert(storeQueue[store_idx].inst); 646 647 store_size = storeQueue[store_idx].size; 648 649 if (store_size == 0) 650 continue; 651 else if (storeQueue[store_idx].inst->uncacheable()) 652 continue; 653
| 598 } 599 600 if (req->isMmappedIpr()) { 601 assert(!load_inst->memData); 602 load_inst->memData = new uint8_t[64]; 603 604 ThreadContext *thread = cpu->tcBase(lsqID); 605 Tick delay; 606 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq); 607 608 if (!TheISA::HasUnalignedMemAcc || !sreqLow) { 609 data_pkt->dataStatic(load_inst->memData); 610 delay = TheISA::handleIprRead(thread, data_pkt); 611 } else { 612 assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr()); 613 PacketPtr fst_data_pkt = new Packet(sreqLow, MemCmd::ReadReq); 614 PacketPtr snd_data_pkt = new Packet(sreqHigh, MemCmd::ReadReq); 615 616 fst_data_pkt->dataStatic(load_inst->memData); 617 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize()); 618 619 delay = TheISA::handleIprRead(thread, fst_data_pkt); 620 unsigned delay2 = TheISA::handleIprRead(thread, snd_data_pkt); 621 if (delay2 > delay) 622 delay = delay2; 623 624 delete sreqLow; 625 delete sreqHigh; 626 delete fst_data_pkt; 627 delete snd_data_pkt; 628 } 629 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this); 630 cpu->schedule(wb, curTick() + delay); 631 return NoFault; 632 } 633 634 while (store_idx != -1) { 635 // End once we've reached the top of the LSQ 636 if (store_idx == storeWBIdx) { 637 break; 638 } 639 640 // Move the index to one younger 641 if (--store_idx < 0) 642 store_idx += SQEntries; 643 644 assert(storeQueue[store_idx].inst); 645 646 store_size = storeQueue[store_idx].size; 647 648 if (store_size == 0) 649 continue; 650 else if (storeQueue[store_idx].inst->uncacheable()) 651 continue; 652
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654 assert(storeQueue[store_idx].inst->effAddrValid);
| 653 assert(storeQueue[store_idx].inst->effAddrValid());
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655 656 // Check if the store data is within the lower and upper bounds of 657 // addresses that the request needs. 658 bool store_has_lower_limit = 659 req->getVaddr() >= storeQueue[store_idx].inst->effAddr; 660 bool store_has_upper_limit = 661 (req->getVaddr() + req->getSize()) <= 662 (storeQueue[store_idx].inst->effAddr + store_size); 663 bool lower_load_has_store_part = 664 req->getVaddr() < (storeQueue[store_idx].inst->effAddr + 665 store_size); 666 bool upper_load_has_store_part = 667 (req->getVaddr() + req->getSize()) > 668 storeQueue[store_idx].inst->effAddr; 669 670 // If the store's data has all of the data needed, we can forward. 671 if ((store_has_lower_limit && store_has_upper_limit)) { 672 // Get shift amount for offset into the store's data. 673 int shift_amt = req->getVaddr() - storeQueue[store_idx].inst->effAddr; 674 675 memcpy(data, storeQueue[store_idx].data + shift_amt, 676 req->getSize()); 677 678 assert(!load_inst->memData); 679 load_inst->memData = new uint8_t[64]; 680 681 memcpy(load_inst->memData, 682 storeQueue[store_idx].data + shift_amt, req->getSize()); 683 684 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to " 685 "addr %#x, data %#x\n", 686 store_idx, req->getVaddr(), data); 687 688 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq); 689 data_pkt->dataStatic(load_inst->memData); 690 691 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this); 692 693 // We'll say this has a 1 cycle load-store forwarding latency 694 // for now. 695 // @todo: Need to make this a parameter. 696 cpu->schedule(wb, curTick()); 697 698 // Don't need to do anything special for split loads. 699 if (TheISA::HasUnalignedMemAcc && sreqLow) { 700 delete sreqLow; 701 delete sreqHigh; 702 } 703 704 ++lsqForwLoads; 705 return NoFault; 706 } else if ((store_has_lower_limit && lower_load_has_store_part) || 707 (store_has_upper_limit && upper_load_has_store_part) || 708 (lower_load_has_store_part && upper_load_has_store_part)) { 709 // This is the partial store-load forwarding case where a store 710 // has only part of the load's data. 711 712 // If it's already been written back, then don't worry about 713 // stalling on it. 714 if (storeQueue[store_idx].completed) { 715 panic("Should not check one of these"); 716 continue; 717 } 718 719 // Must stall load and force it to retry, so long as it's the oldest 720 // load that needs to do so. 721 if (!stalled || 722 (stalled && 723 load_inst->seqNum < 724 loadQueue[stallingLoadIdx]->seqNum)) { 725 stalled = true; 726 stallingStoreIsn = storeQueue[store_idx].inst->seqNum; 727 stallingLoadIdx = load_idx; 728 } 729 730 // Tell IQ/mem dep unit that this instruction will need to be 731 // rescheduled eventually 732 iewStage->rescheduleMemInst(load_inst); 733 iewStage->decrWb(load_inst->seqNum); 734 load_inst->clearIssued(); 735 ++lsqRescheduledLoads; 736 737 // Do not generate a writeback event as this instruction is not 738 // complete. 739 DPRINTF(LSQUnit, "Load-store forwarding mis-match. " 740 "Store idx %i to load addr %#x\n", 741 store_idx, req->getVaddr()); 742 743 // Must delete request now that it wasn't handed off to 744 // memory. This is quite ugly. @todo: Figure out the 745 // proper place to really handle request deletes. 746 delete req; 747 if (TheISA::HasUnalignedMemAcc && sreqLow) { 748 delete sreqLow; 749 delete sreqHigh; 750 } 751 752 return NoFault; 753 } 754 } 755 756 // If there's no forwarding case, then go access memory 757 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %s\n", 758 load_inst->seqNum, load_inst->pcState()); 759 760 assert(!load_inst->memData); 761 load_inst->memData = new uint8_t[64]; 762 763 ++usedPorts; 764 765 // if we the cache is not blocked, do cache access 766 bool completedFirst = false; 767 if (!lsq->cacheBlocked()) { 768 MemCmd command = 769 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq; 770 PacketPtr data_pkt = new Packet(req, command); 771 PacketPtr fst_data_pkt = NULL; 772 PacketPtr snd_data_pkt = NULL; 773 774 data_pkt->dataStatic(load_inst->memData); 775 776 LSQSenderState *state = new LSQSenderState; 777 state->isLoad = true; 778 state->idx = load_idx; 779 state->inst = load_inst; 780 data_pkt->senderState = state; 781 782 if (!TheISA::HasUnalignedMemAcc || !sreqLow) { 783 784 // Point the first packet at the main data packet. 785 fst_data_pkt = data_pkt; 786 } else { 787 788 // Create the split packets. 789 fst_data_pkt = new Packet(sreqLow, command); 790 snd_data_pkt = new Packet(sreqHigh, command); 791 792 fst_data_pkt->dataStatic(load_inst->memData); 793 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize()); 794 795 fst_data_pkt->senderState = state; 796 snd_data_pkt->senderState = state; 797 798 state->isSplit = true; 799 state->outstanding = 2; 800 state->mainPkt = data_pkt; 801 } 802 803 if (!dcachePort->sendTimingReq(fst_data_pkt)) { 804 // Delete state and data packet because a load retry 805 // initiates a pipeline restart; it does not retry. 806 delete state; 807 delete data_pkt->req; 808 delete data_pkt; 809 if (TheISA::HasUnalignedMemAcc && sreqLow) { 810 delete fst_data_pkt->req; 811 delete fst_data_pkt; 812 delete snd_data_pkt->req; 813 delete snd_data_pkt; 814 sreqLow = NULL; 815 sreqHigh = NULL; 816 } 817 818 req = NULL; 819 820 // If the access didn't succeed, tell the LSQ by setting 821 // the retry thread id. 822 lsq->setRetryTid(lsqID); 823 } else if (TheISA::HasUnalignedMemAcc && sreqLow) { 824 completedFirst = true; 825 826 // The first packet was sent without problems, so send this one 827 // too. If there is a problem with this packet then the whole 828 // load will be squashed, so indicate this to the state object. 829 // The first packet will return in completeDataAccess and be 830 // handled there. 831 ++usedPorts; 832 if (!dcachePort->sendTimingReq(snd_data_pkt)) { 833 834 // The main packet will be deleted in completeDataAccess. 835 delete snd_data_pkt->req; 836 delete snd_data_pkt; 837 838 state->complete(); 839 840 req = NULL; 841 sreqHigh = NULL; 842 843 lsq->setRetryTid(lsqID); 844 } 845 } 846 } 847 848 // If the cache was blocked, or has become blocked due to the access, 849 // handle it. 850 if (lsq->cacheBlocked()) { 851 if (req) 852 delete req; 853 if (TheISA::HasUnalignedMemAcc && sreqLow && !completedFirst) { 854 delete sreqLow; 855 delete sreqHigh; 856 } 857 858 ++lsqCacheBlocked; 859 860 // If the first part of a split access succeeds, then let the LSQ 861 // handle the decrWb when completeDataAccess is called upon return 862 // of the requested first part of data 863 if (!completedFirst) 864 iewStage->decrWb(load_inst->seqNum); 865 866 // There's an older load that's already going to squash. 867 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum) 868 return NoFault; 869 870 // Record that the load was blocked due to memory. This 871 // load will squash all instructions after it, be 872 // refetched, and re-executed. 873 isLoadBlocked = true; 874 loadBlockedHandled = false; 875 blockedLoadSeqNum = load_inst->seqNum; 876 // No fault occurred, even though the interface is blocked. 877 return NoFault; 878 } 879 880 return NoFault; 881} 882 883template <class Impl> 884Fault 885LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh, 886 uint8_t *data, int store_idx) 887{ 888 assert(storeQueue[store_idx].inst); 889 890 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x" 891 " | storeHead:%i [sn:%i]\n", 892 store_idx, req->getPaddr(), data, storeHead, 893 storeQueue[store_idx].inst->seqNum); 894 895 storeQueue[store_idx].req = req; 896 storeQueue[store_idx].sreqLow = sreqLow; 897 storeQueue[store_idx].sreqHigh = sreqHigh; 898 unsigned size = req->getSize(); 899 storeQueue[store_idx].size = size; 900 assert(size <= sizeof(storeQueue[store_idx].data)); 901 902 // Split stores can only occur in ISAs with unaligned memory accesses. If 903 // a store request has been split, sreqLow and sreqHigh will be non-null. 904 if (TheISA::HasUnalignedMemAcc && sreqLow) { 905 storeQueue[store_idx].isSplit = true; 906 } 907 908 memcpy(storeQueue[store_idx].data, data, size); 909 910 // This function only writes the data to the store queue, so no fault 911 // can happen here. 912 return NoFault; 913} 914 915#endif // __CPU_O3_LSQ_UNIT_HH__
| 654 655 // Check if the store data is within the lower and upper bounds of 656 // addresses that the request needs. 657 bool store_has_lower_limit = 658 req->getVaddr() >= storeQueue[store_idx].inst->effAddr; 659 bool store_has_upper_limit = 660 (req->getVaddr() + req->getSize()) <= 661 (storeQueue[store_idx].inst->effAddr + store_size); 662 bool lower_load_has_store_part = 663 req->getVaddr() < (storeQueue[store_idx].inst->effAddr + 664 store_size); 665 bool upper_load_has_store_part = 666 (req->getVaddr() + req->getSize()) > 667 storeQueue[store_idx].inst->effAddr; 668 669 // If the store's data has all of the data needed, we can forward. 670 if ((store_has_lower_limit && store_has_upper_limit)) { 671 // Get shift amount for offset into the store's data. 672 int shift_amt = req->getVaddr() - storeQueue[store_idx].inst->effAddr; 673 674 memcpy(data, storeQueue[store_idx].data + shift_amt, 675 req->getSize()); 676 677 assert(!load_inst->memData); 678 load_inst->memData = new uint8_t[64]; 679 680 memcpy(load_inst->memData, 681 storeQueue[store_idx].data + shift_amt, req->getSize()); 682 683 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to " 684 "addr %#x, data %#x\n", 685 store_idx, req->getVaddr(), data); 686 687 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq); 688 data_pkt->dataStatic(load_inst->memData); 689 690 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this); 691 692 // We'll say this has a 1 cycle load-store forwarding latency 693 // for now. 694 // @todo: Need to make this a parameter. 695 cpu->schedule(wb, curTick()); 696 697 // Don't need to do anything special for split loads. 698 if (TheISA::HasUnalignedMemAcc && sreqLow) { 699 delete sreqLow; 700 delete sreqHigh; 701 } 702 703 ++lsqForwLoads; 704 return NoFault; 705 } else if ((store_has_lower_limit && lower_load_has_store_part) || 706 (store_has_upper_limit && upper_load_has_store_part) || 707 (lower_load_has_store_part && upper_load_has_store_part)) { 708 // This is the partial store-load forwarding case where a store 709 // has only part of the load's data. 710 711 // If it's already been written back, then don't worry about 712 // stalling on it. 713 if (storeQueue[store_idx].completed) { 714 panic("Should not check one of these"); 715 continue; 716 } 717 718 // Must stall load and force it to retry, so long as it's the oldest 719 // load that needs to do so. 720 if (!stalled || 721 (stalled && 722 load_inst->seqNum < 723 loadQueue[stallingLoadIdx]->seqNum)) { 724 stalled = true; 725 stallingStoreIsn = storeQueue[store_idx].inst->seqNum; 726 stallingLoadIdx = load_idx; 727 } 728 729 // Tell IQ/mem dep unit that this instruction will need to be 730 // rescheduled eventually 731 iewStage->rescheduleMemInst(load_inst); 732 iewStage->decrWb(load_inst->seqNum); 733 load_inst->clearIssued(); 734 ++lsqRescheduledLoads; 735 736 // Do not generate a writeback event as this instruction is not 737 // complete. 738 DPRINTF(LSQUnit, "Load-store forwarding mis-match. " 739 "Store idx %i to load addr %#x\n", 740 store_idx, req->getVaddr()); 741 742 // Must delete request now that it wasn't handed off to 743 // memory. This is quite ugly. @todo: Figure out the 744 // proper place to really handle request deletes. 745 delete req; 746 if (TheISA::HasUnalignedMemAcc && sreqLow) { 747 delete sreqLow; 748 delete sreqHigh; 749 } 750 751 return NoFault; 752 } 753 } 754 755 // If there's no forwarding case, then go access memory 756 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %s\n", 757 load_inst->seqNum, load_inst->pcState()); 758 759 assert(!load_inst->memData); 760 load_inst->memData = new uint8_t[64]; 761 762 ++usedPorts; 763 764 // if we the cache is not blocked, do cache access 765 bool completedFirst = false; 766 if (!lsq->cacheBlocked()) { 767 MemCmd command = 768 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq; 769 PacketPtr data_pkt = new Packet(req, command); 770 PacketPtr fst_data_pkt = NULL; 771 PacketPtr snd_data_pkt = NULL; 772 773 data_pkt->dataStatic(load_inst->memData); 774 775 LSQSenderState *state = new LSQSenderState; 776 state->isLoad = true; 777 state->idx = load_idx; 778 state->inst = load_inst; 779 data_pkt->senderState = state; 780 781 if (!TheISA::HasUnalignedMemAcc || !sreqLow) { 782 783 // Point the first packet at the main data packet. 784 fst_data_pkt = data_pkt; 785 } else { 786 787 // Create the split packets. 788 fst_data_pkt = new Packet(sreqLow, command); 789 snd_data_pkt = new Packet(sreqHigh, command); 790 791 fst_data_pkt->dataStatic(load_inst->memData); 792 snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize()); 793 794 fst_data_pkt->senderState = state; 795 snd_data_pkt->senderState = state; 796 797 state->isSplit = true; 798 state->outstanding = 2; 799 state->mainPkt = data_pkt; 800 } 801 802 if (!dcachePort->sendTimingReq(fst_data_pkt)) { 803 // Delete state and data packet because a load retry 804 // initiates a pipeline restart; it does not retry. 805 delete state; 806 delete data_pkt->req; 807 delete data_pkt; 808 if (TheISA::HasUnalignedMemAcc && sreqLow) { 809 delete fst_data_pkt->req; 810 delete fst_data_pkt; 811 delete snd_data_pkt->req; 812 delete snd_data_pkt; 813 sreqLow = NULL; 814 sreqHigh = NULL; 815 } 816 817 req = NULL; 818 819 // If the access didn't succeed, tell the LSQ by setting 820 // the retry thread id. 821 lsq->setRetryTid(lsqID); 822 } else if (TheISA::HasUnalignedMemAcc && sreqLow) { 823 completedFirst = true; 824 825 // The first packet was sent without problems, so send this one 826 // too. If there is a problem with this packet then the whole 827 // load will be squashed, so indicate this to the state object. 828 // The first packet will return in completeDataAccess and be 829 // handled there. 830 ++usedPorts; 831 if (!dcachePort->sendTimingReq(snd_data_pkt)) { 832 833 // The main packet will be deleted in completeDataAccess. 834 delete snd_data_pkt->req; 835 delete snd_data_pkt; 836 837 state->complete(); 838 839 req = NULL; 840 sreqHigh = NULL; 841 842 lsq->setRetryTid(lsqID); 843 } 844 } 845 } 846 847 // If the cache was blocked, or has become blocked due to the access, 848 // handle it. 849 if (lsq->cacheBlocked()) { 850 if (req) 851 delete req; 852 if (TheISA::HasUnalignedMemAcc && sreqLow && !completedFirst) { 853 delete sreqLow; 854 delete sreqHigh; 855 } 856 857 ++lsqCacheBlocked; 858 859 // If the first part of a split access succeeds, then let the LSQ 860 // handle the decrWb when completeDataAccess is called upon return 861 // of the requested first part of data 862 if (!completedFirst) 863 iewStage->decrWb(load_inst->seqNum); 864 865 // There's an older load that's already going to squash. 866 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum) 867 return NoFault; 868 869 // Record that the load was blocked due to memory. This 870 // load will squash all instructions after it, be 871 // refetched, and re-executed. 872 isLoadBlocked = true; 873 loadBlockedHandled = false; 874 blockedLoadSeqNum = load_inst->seqNum; 875 // No fault occurred, even though the interface is blocked. 876 return NoFault; 877 } 878 879 return NoFault; 880} 881 882template <class Impl> 883Fault 884LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh, 885 uint8_t *data, int store_idx) 886{ 887 assert(storeQueue[store_idx].inst); 888 889 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x" 890 " | storeHead:%i [sn:%i]\n", 891 store_idx, req->getPaddr(), data, storeHead, 892 storeQueue[store_idx].inst->seqNum); 893 894 storeQueue[store_idx].req = req; 895 storeQueue[store_idx].sreqLow = sreqLow; 896 storeQueue[store_idx].sreqHigh = sreqHigh; 897 unsigned size = req->getSize(); 898 storeQueue[store_idx].size = size; 899 assert(size <= sizeof(storeQueue[store_idx].data)); 900 901 // Split stores can only occur in ISAs with unaligned memory accesses. If 902 // a store request has been split, sreqLow and sreqHigh will be non-null. 903 if (TheISA::HasUnalignedMemAcc && sreqLow) { 904 storeQueue[store_idx].isSplit = true; 905 } 906 907 memcpy(storeQueue[store_idx].data, data, size); 908 909 // This function only writes the data to the store queue, so no fault 910 // can happen here. 911 return NoFault; 912} 913 914#endif // __CPU_O3_LSQ_UNIT_HH__
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