1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_LSQ_UNIT_HH__
33#define __CPU_O3_LSQ_UNIT_HH__
34
35#include <algorithm>
36#include <map>
37#include <queue>
38
39#include "arch/faults.hh"
40#include "arch/locked_mem.hh"
41#include "config/full_system.hh"
42#include "base/hashmap.hh"
43#include "cpu/inst_seq.hh"
44#include "mem/packet.hh"
45#include "mem/port.hh"
46
47/**
48 * Class that implements the actual LQ and SQ for each specific
49 * thread. Both are circular queues; load entries are freed upon
50 * committing, while store entries are freed once they writeback. The
51 * LSQUnit tracks if there are memory ordering violations, and also
52 * detects partial load to store forwarding cases (a store only has
53 * part of a load's data) that requires the load to wait until the
54 * store writes back. In the former case it holds onto the instruction
55 * until the dependence unit looks at it, and in the latter it stalls
56 * the LSQ until the store writes back. At that point the load is
57 * replayed.
58 */
59template <class Impl>
60class LSQUnit {
61 protected:
62 typedef TheISA::IntReg IntReg;
63 public:
64 typedef typename Impl::Params Params;
65 typedef typename Impl::O3CPU O3CPU;
66 typedef typename Impl::DynInstPtr DynInstPtr;
67 typedef typename Impl::CPUPol::IEW IEW;
68 typedef typename Impl::CPUPol::LSQ LSQ;
69 typedef typename Impl::CPUPol::IssueStruct IssueStruct;
70
71 public:
72 /** Constructs an LSQ unit. init() must be called prior to use. */
73 LSQUnit();
74
75 /** Initializes the LSQ unit with the specified number of entries. */
76 void init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
77 unsigned maxSQEntries, unsigned id);
78
79 /** Returns the name of the LSQ unit. */
80 std::string name() const;
81
82 /** Registers statistics. */
83 void regStats();
84
85 /** Sets the CPU pointer. */
86 void setCPU(O3CPU *cpu_ptr);
87
88 /** Sets the IEW stage pointer. */
89 void setIEW(IEW *iew_ptr)
90 { iewStage = iew_ptr; }
91
92 /** Sets the pointer to the dcache port. */
93 void setDcachePort(Port *dcache_port)
94 { dcachePort = dcache_port; }
95
96 /** Switches out LSQ unit. */
97 void switchOut();
98
99 /** Takes over from another CPU's thread. */
100 void takeOverFrom();
101
102 /** Returns if the LSQ is switched out. */
103 bool isSwitchedOut() { return switchedOut; }
104
105 /** Ticks the LSQ unit, which in this case only resets the number of
106 * used cache ports.
107 * @todo: Move the number of used ports up to the LSQ level so it can
108 * be shared by all LSQ units.
109 */
110 void tick() { usedPorts = 0; }
111
112 /** Inserts an instruction. */
113 void insert(DynInstPtr &inst);
114 /** Inserts a load instruction. */
115 void insertLoad(DynInstPtr &load_inst);
116 /** Inserts a store instruction. */
117 void insertStore(DynInstPtr &store_inst);
118
119 /** Executes a load instruction. */
120 Fault executeLoad(DynInstPtr &inst);
121
122 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
123 /** Executes a store instruction. */
124 Fault executeStore(DynInstPtr &inst);
125
126 /** Commits the head load. */
127 void commitLoad();
128 /** Commits loads older than a specific sequence number. */
129 void commitLoads(InstSeqNum &youngest_inst);
130
131 /** Commits stores older than a specific sequence number. */
132 void commitStores(InstSeqNum &youngest_inst);
133
134 /** Writes back stores. */
135 void writebackStores();
136
137 /** Completes the data access that has been returned from the
138 * memory system. */
139 void completeDataAccess(PacketPtr pkt);
140
141 /** Clears all the entries in the LQ. */
142 void clearLQ();
143
144 /** Clears all the entries in the SQ. */
145 void clearSQ();
146
147 /** Resizes the LQ to a given size. */
148 void resizeLQ(unsigned size);
149
150 /** Resizes the SQ to a given size. */
151 void resizeSQ(unsigned size);
152
153 /** Squashes all instructions younger than a specific sequence number. */
154 void squash(const InstSeqNum &squashed_num);
155
156 /** Returns if there is a memory ordering violation. Value is reset upon
157 * call to getMemDepViolator().
158 */
159 bool violation() { return memDepViolator; }
160
161 /** Returns the memory ordering violator. */
162 DynInstPtr getMemDepViolator();
163
164 /** Returns if a load became blocked due to the memory system. */
165 bool loadBlocked()
166 { return isLoadBlocked; }
167
168 /** Clears the signal that a load became blocked. */
169 void clearLoadBlocked()
170 { isLoadBlocked = false; }
171
172 /** Returns if the blocked load was handled. */
173 bool isLoadBlockedHandled()
174 { return loadBlockedHandled; }
175
176 /** Records the blocked load as being handled. */
177 void setLoadBlockedHandled()
178 { loadBlockedHandled = true; }
179
180 /** Returns the number of free entries (min of free LQ and SQ entries). */
181 unsigned numFreeEntries();
182
183 /** Returns the number of loads ready to execute. */
184 int numLoadsReady();
185
186 /** Returns the number of loads in the LQ. */
187 int numLoads() { return loads; }
188
189 /** Returns the number of stores in the SQ. */
190 int numStores() { return stores; }
191
192 /** Returns if either the LQ or SQ is full. */
193 bool isFull() { return lqFull() || sqFull(); }
194
195 /** Returns if the LQ is full. */
196 bool lqFull() { return loads >= (LQEntries - 1); }
197
198 /** Returns if the SQ is full. */
199 bool sqFull() { return stores >= (SQEntries - 1); }
200
201 /** Returns the number of instructions in the LSQ. */
202 unsigned getCount() { return loads + stores; }
203
204 /** Returns if there are any stores to writeback. */
205 bool hasStoresToWB() { return storesToWB; }
206
207 /** Returns the number of stores to writeback. */
208 int numStoresToWB() { return storesToWB; }
209
210 /** Returns if the LSQ unit will writeback on this cycle. */
211 bool willWB() { return storeQueue[storeWBIdx].canWB &&
212 !storeQueue[storeWBIdx].completed &&
213 !isStoreBlocked; }
214
215 /** Handles doing the retry. */
216 void recvRetry();
217
218 private:
219 /** Writes back the instruction, sending it to IEW. */
220 void writeback(DynInstPtr &inst, PacketPtr pkt);
221
222 /** Handles completing the send of a store to memory. */
223 void storePostSend(PacketPtr pkt);
224
225 /** Completes the store at the specified index. */
226 void completeStore(int store_idx);
227
228 /** Increments the given store index (circular queue). */
229 inline void incrStIdx(int &store_idx);
230 /** Decrements the given store index (circular queue). */
231 inline void decrStIdx(int &store_idx);
232 /** Increments the given load index (circular queue). */
233 inline void incrLdIdx(int &load_idx);
234 /** Decrements the given load index (circular queue). */
235 inline void decrLdIdx(int &load_idx);
236
237 public:
238 /** Debugging function to dump instructions in the LSQ. */
239 void dumpInsts();
240
241 private:
242 /** Pointer to the CPU. */
243 O3CPU *cpu;
244
245 /** Pointer to the IEW stage. */
246 IEW *iewStage;
247
248 /** Pointer to the LSQ. */
249 LSQ *lsq;
250
251 /** Pointer to the dcache port. Used only for sending. */
252 Port *dcachePort;
253
254 /** Derived class to hold any sender state the LSQ needs. */
255 class LSQSenderState : public Packet::SenderState
256 {
257 public:
258 /** Default constructor. */
259 LSQSenderState()
260 : noWB(false)
261 { }
262
263 /** Instruction who initiated the access to memory. */
264 DynInstPtr inst;
265 /** Whether or not it is a load. */
266 bool isLoad;
267 /** The LQ/SQ index of the instruction. */
268 int idx;
269 /** Whether or not the instruction will need to writeback. */
270 bool noWB;
271 };
272
273 /** Writeback event, specifically for when stores forward data to loads. */
274 class WritebackEvent : public Event {
275 public:
276 /** Constructs a writeback event. */
277 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr);
278
279 /** Processes the writeback event. */
280 void process();
281
282 /** Returns the description of this event. */
283 const char *description();
284
285 private:
286 /** Instruction whose results are being written back. */
287 DynInstPtr inst;
288
289 /** The packet that would have been sent to memory. */
290 PacketPtr pkt;
291
292 /** The pointer to the LSQ unit that issued the store. */
293 LSQUnit<Impl> *lsqPtr;
294 };
295
296 public:
297 struct SQEntry {
298 /** Constructs an empty store queue entry. */
299 SQEntry()
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_LSQ_UNIT_HH__
33#define __CPU_O3_LSQ_UNIT_HH__
34
35#include <algorithm>
36#include <map>
37#include <queue>
38
39#include "arch/faults.hh"
40#include "arch/locked_mem.hh"
41#include "config/full_system.hh"
42#include "base/hashmap.hh"
43#include "cpu/inst_seq.hh"
44#include "mem/packet.hh"
45#include "mem/port.hh"
46
47/**
48 * Class that implements the actual LQ and SQ for each specific
49 * thread. Both are circular queues; load entries are freed upon
50 * committing, while store entries are freed once they writeback. The
51 * LSQUnit tracks if there are memory ordering violations, and also
52 * detects partial load to store forwarding cases (a store only has
53 * part of a load's data) that requires the load to wait until the
54 * store writes back. In the former case it holds onto the instruction
55 * until the dependence unit looks at it, and in the latter it stalls
56 * the LSQ until the store writes back. At that point the load is
57 * replayed.
58 */
59template <class Impl>
60class LSQUnit {
61 protected:
62 typedef TheISA::IntReg IntReg;
63 public:
64 typedef typename Impl::Params Params;
65 typedef typename Impl::O3CPU O3CPU;
66 typedef typename Impl::DynInstPtr DynInstPtr;
67 typedef typename Impl::CPUPol::IEW IEW;
68 typedef typename Impl::CPUPol::LSQ LSQ;
69 typedef typename Impl::CPUPol::IssueStruct IssueStruct;
70
71 public:
72 /** Constructs an LSQ unit. init() must be called prior to use. */
73 LSQUnit();
74
75 /** Initializes the LSQ unit with the specified number of entries. */
76 void init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
77 unsigned maxSQEntries, unsigned id);
78
79 /** Returns the name of the LSQ unit. */
80 std::string name() const;
81
82 /** Registers statistics. */
83 void regStats();
84
85 /** Sets the CPU pointer. */
86 void setCPU(O3CPU *cpu_ptr);
87
88 /** Sets the IEW stage pointer. */
89 void setIEW(IEW *iew_ptr)
90 { iewStage = iew_ptr; }
91
92 /** Sets the pointer to the dcache port. */
93 void setDcachePort(Port *dcache_port)
94 { dcachePort = dcache_port; }
95
96 /** Switches out LSQ unit. */
97 void switchOut();
98
99 /** Takes over from another CPU's thread. */
100 void takeOverFrom();
101
102 /** Returns if the LSQ is switched out. */
103 bool isSwitchedOut() { return switchedOut; }
104
105 /** Ticks the LSQ unit, which in this case only resets the number of
106 * used cache ports.
107 * @todo: Move the number of used ports up to the LSQ level so it can
108 * be shared by all LSQ units.
109 */
110 void tick() { usedPorts = 0; }
111
112 /** Inserts an instruction. */
113 void insert(DynInstPtr &inst);
114 /** Inserts a load instruction. */
115 void insertLoad(DynInstPtr &load_inst);
116 /** Inserts a store instruction. */
117 void insertStore(DynInstPtr &store_inst);
118
119 /** Executes a load instruction. */
120 Fault executeLoad(DynInstPtr &inst);
121
122 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
123 /** Executes a store instruction. */
124 Fault executeStore(DynInstPtr &inst);
125
126 /** Commits the head load. */
127 void commitLoad();
128 /** Commits loads older than a specific sequence number. */
129 void commitLoads(InstSeqNum &youngest_inst);
130
131 /** Commits stores older than a specific sequence number. */
132 void commitStores(InstSeqNum &youngest_inst);
133
134 /** Writes back stores. */
135 void writebackStores();
136
137 /** Completes the data access that has been returned from the
138 * memory system. */
139 void completeDataAccess(PacketPtr pkt);
140
141 /** Clears all the entries in the LQ. */
142 void clearLQ();
143
144 /** Clears all the entries in the SQ. */
145 void clearSQ();
146
147 /** Resizes the LQ to a given size. */
148 void resizeLQ(unsigned size);
149
150 /** Resizes the SQ to a given size. */
151 void resizeSQ(unsigned size);
152
153 /** Squashes all instructions younger than a specific sequence number. */
154 void squash(const InstSeqNum &squashed_num);
155
156 /** Returns if there is a memory ordering violation. Value is reset upon
157 * call to getMemDepViolator().
158 */
159 bool violation() { return memDepViolator; }
160
161 /** Returns the memory ordering violator. */
162 DynInstPtr getMemDepViolator();
163
164 /** Returns if a load became blocked due to the memory system. */
165 bool loadBlocked()
166 { return isLoadBlocked; }
167
168 /** Clears the signal that a load became blocked. */
169 void clearLoadBlocked()
170 { isLoadBlocked = false; }
171
172 /** Returns if the blocked load was handled. */
173 bool isLoadBlockedHandled()
174 { return loadBlockedHandled; }
175
176 /** Records the blocked load as being handled. */
177 void setLoadBlockedHandled()
178 { loadBlockedHandled = true; }
179
180 /** Returns the number of free entries (min of free LQ and SQ entries). */
181 unsigned numFreeEntries();
182
183 /** Returns the number of loads ready to execute. */
184 int numLoadsReady();
185
186 /** Returns the number of loads in the LQ. */
187 int numLoads() { return loads; }
188
189 /** Returns the number of stores in the SQ. */
190 int numStores() { return stores; }
191
192 /** Returns if either the LQ or SQ is full. */
193 bool isFull() { return lqFull() || sqFull(); }
194
195 /** Returns if the LQ is full. */
196 bool lqFull() { return loads >= (LQEntries - 1); }
197
198 /** Returns if the SQ is full. */
199 bool sqFull() { return stores >= (SQEntries - 1); }
200
201 /** Returns the number of instructions in the LSQ. */
202 unsigned getCount() { return loads + stores; }
203
204 /** Returns if there are any stores to writeback. */
205 bool hasStoresToWB() { return storesToWB; }
206
207 /** Returns the number of stores to writeback. */
208 int numStoresToWB() { return storesToWB; }
209
210 /** Returns if the LSQ unit will writeback on this cycle. */
211 bool willWB() { return storeQueue[storeWBIdx].canWB &&
212 !storeQueue[storeWBIdx].completed &&
213 !isStoreBlocked; }
214
215 /** Handles doing the retry. */
216 void recvRetry();
217
218 private:
219 /** Writes back the instruction, sending it to IEW. */
220 void writeback(DynInstPtr &inst, PacketPtr pkt);
221
222 /** Handles completing the send of a store to memory. */
223 void storePostSend(PacketPtr pkt);
224
225 /** Completes the store at the specified index. */
226 void completeStore(int store_idx);
227
228 /** Increments the given store index (circular queue). */
229 inline void incrStIdx(int &store_idx);
230 /** Decrements the given store index (circular queue). */
231 inline void decrStIdx(int &store_idx);
232 /** Increments the given load index (circular queue). */
233 inline void incrLdIdx(int &load_idx);
234 /** Decrements the given load index (circular queue). */
235 inline void decrLdIdx(int &load_idx);
236
237 public:
238 /** Debugging function to dump instructions in the LSQ. */
239 void dumpInsts();
240
241 private:
242 /** Pointer to the CPU. */
243 O3CPU *cpu;
244
245 /** Pointer to the IEW stage. */
246 IEW *iewStage;
247
248 /** Pointer to the LSQ. */
249 LSQ *lsq;
250
251 /** Pointer to the dcache port. Used only for sending. */
252 Port *dcachePort;
253
254 /** Derived class to hold any sender state the LSQ needs. */
255 class LSQSenderState : public Packet::SenderState
256 {
257 public:
258 /** Default constructor. */
259 LSQSenderState()
260 : noWB(false)
261 { }
262
263 /** Instruction who initiated the access to memory. */
264 DynInstPtr inst;
265 /** Whether or not it is a load. */
266 bool isLoad;
267 /** The LQ/SQ index of the instruction. */
268 int idx;
269 /** Whether or not the instruction will need to writeback. */
270 bool noWB;
271 };
272
273 /** Writeback event, specifically for when stores forward data to loads. */
274 class WritebackEvent : public Event {
275 public:
276 /** Constructs a writeback event. */
277 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr);
278
279 /** Processes the writeback event. */
280 void process();
281
282 /** Returns the description of this event. */
283 const char *description();
284
285 private:
286 /** Instruction whose results are being written back. */
287 DynInstPtr inst;
288
289 /** The packet that would have been sent to memory. */
290 PacketPtr pkt;
291
292 /** The pointer to the LSQ unit that issued the store. */
293 LSQUnit<Impl> *lsqPtr;
294 };
295
296 public:
297 struct SQEntry {
298 /** Constructs an empty store queue entry. */
299 SQEntry()
|
300 : inst(NULL), req(NULL), size(0), data(0),
| 300 : inst(NULL), req(NULL), size(0),
|
301 canWB(0), committed(0), completed(0)
| 301 canWB(0), committed(0), completed(0)
|
302 { }
| 302 {
303 bzero(data, sizeof(data));
304 }
|
303
304 /** Constructs a store queue entry for a given instruction. */
305 SQEntry(DynInstPtr &_inst)
| 305
306 /** Constructs a store queue entry for a given instruction. */
307 SQEntry(DynInstPtr &_inst)
|
306 : inst(_inst), req(NULL), size(0), data(0),
| 308 : inst(_inst), req(NULL), size(0),
|
307 canWB(0), committed(0), completed(0)
| 309 canWB(0), committed(0), completed(0)
|
308 { }
| 310 {
311 bzero(data, sizeof(data));
312 }
|
309
310 /** The store instruction. */
311 DynInstPtr inst;
312 /** The request for the store. */
313 RequestPtr req;
314 /** The size of the store. */
315 int size;
316 /** The store data. */
| 313
314 /** The store instruction. */
315 DynInstPtr inst;
316 /** The request for the store. */
317 RequestPtr req;
318 /** The size of the store. */
319 int size;
320 /** The store data. */
|
317 IntReg data;
| 321 char data[sizeof(IntReg)];
|
318 /** Whether or not the store can writeback. */
319 bool canWB;
320 /** Whether or not the store is committed. */
321 bool committed;
322 /** Whether or not the store is completed. */
323 bool completed;
324 };
325
326 private:
327 /** The LSQUnit thread id. */
328 unsigned lsqID;
329
330 /** The store queue. */
331 std::vector<SQEntry> storeQueue;
332
333 /** The load queue. */
334 std::vector<DynInstPtr> loadQueue;
335
336 /** The number of LQ entries, plus a sentinel entry (circular queue).
337 * @todo: Consider having var that records the true number of LQ entries.
338 */
339 unsigned LQEntries;
340 /** The number of SQ entries, plus a sentinel entry (circular queue).
341 * @todo: Consider having var that records the true number of SQ entries.
342 */
343 unsigned SQEntries;
344
345 /** The number of load instructions in the LQ. */
346 int loads;
347 /** The number of store instructions in the SQ. */
348 int stores;
349 /** The number of store instructions in the SQ waiting to writeback. */
350 int storesToWB;
351
352 /** The index of the head instruction in the LQ. */
353 int loadHead;
354 /** The index of the tail instruction in the LQ. */
355 int loadTail;
356
357 /** The index of the head instruction in the SQ. */
358 int storeHead;
359 /** The index of the first instruction that may be ready to be
360 * written back, and has not yet been written back.
361 */
362 int storeWBIdx;
363 /** The index of the tail instruction in the SQ. */
364 int storeTail;
365
366 /// @todo Consider moving to a more advanced model with write vs read ports
367 /** The number of cache ports available each cycle. */
368 int cachePorts;
369
370 /** The number of used cache ports in this cycle. */
371 int usedPorts;
372
373 /** Is the LSQ switched out. */
374 bool switchedOut;
375
376 //list<InstSeqNum> mshrSeqNums;
377
378 /** Wire to read information from the issue stage time queue. */
379 typename TimeBuffer<IssueStruct>::wire fromIssue;
380
381 /** Whether or not the LSQ is stalled. */
382 bool stalled;
383 /** The store that causes the stall due to partial store to load
384 * forwarding.
385 */
386 InstSeqNum stallingStoreIsn;
387 /** The index of the above store. */
388 int stallingLoadIdx;
389
390 /** The packet that needs to be retried. */
391 PacketPtr retryPkt;
392
393 /** Whehter or not a store is blocked due to the memory system. */
394 bool isStoreBlocked;
395
396 /** Whether or not a load is blocked due to the memory system. */
397 bool isLoadBlocked;
398
399 /** Has the blocked load been handled. */
400 bool loadBlockedHandled;
401
402 /** The sequence number of the blocked load. */
403 InstSeqNum blockedLoadSeqNum;
404
405 /** The oldest load that caused a memory ordering violation. */
406 DynInstPtr memDepViolator;
407
408 // Will also need how many read/write ports the Dcache has. Or keep track
409 // of that in stage that is one level up, and only call executeLoad/Store
410 // the appropriate number of times.
411 /** Total number of loads forwaded from LSQ stores. */
412 Stats::Scalar<> lsqForwLoads;
413
414 /** Total number of loads ignored due to invalid addresses. */
415 Stats::Scalar<> invAddrLoads;
416
417 /** Total number of squashed loads. */
418 Stats::Scalar<> lsqSquashedLoads;
419
420 /** Total number of responses from the memory system that are
421 * ignored due to the instruction already being squashed. */
422 Stats::Scalar<> lsqIgnoredResponses;
423
424 /** Tota number of memory ordering violations. */
425 Stats::Scalar<> lsqMemOrderViolation;
426
427 /** Total number of squashed stores. */
428 Stats::Scalar<> lsqSquashedStores;
429
430 /** Total number of software prefetches ignored due to invalid addresses. */
431 Stats::Scalar<> invAddrSwpfs;
432
433 /** Ready loads blocked due to partial store-forwarding. */
434 Stats::Scalar<> lsqBlockedLoads;
435
436 /** Number of loads that were rescheduled. */
437 Stats::Scalar<> lsqRescheduledLoads;
438
439 /** Number of times the LSQ is blocked due to the cache. */
440 Stats::Scalar<> lsqCacheBlocked;
441
442 public:
443 /** Executes the load at the given index. */
444 template <class T>
445 Fault read(Request *req, T &data, int load_idx);
446
447 /** Executes the store at the given index. */
448 template <class T>
449 Fault write(Request *req, T &data, int store_idx);
450
451 /** Returns the index of the head load instruction. */
452 int getLoadHead() { return loadHead; }
453 /** Returns the sequence number of the head load instruction. */
454 InstSeqNum getLoadHeadSeqNum()
455 {
456 if (loadQueue[loadHead]) {
457 return loadQueue[loadHead]->seqNum;
458 } else {
459 return 0;
460 }
461
462 }
463
464 /** Returns the index of the head store instruction. */
465 int getStoreHead() { return storeHead; }
466 /** Returns the sequence number of the head store instruction. */
467 InstSeqNum getStoreHeadSeqNum()
468 {
469 if (storeQueue[storeHead].inst) {
470 return storeQueue[storeHead].inst->seqNum;
471 } else {
472 return 0;
473 }
474
475 }
476
477 /** Returns whether or not the LSQ unit is stalled. */
478 bool isStalled() { return stalled; }
479};
480
481template <class Impl>
482template <class T>
483Fault
484LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
485{
486 DynInstPtr load_inst = loadQueue[load_idx];
487
488 assert(load_inst);
489
490 assert(!load_inst->isExecuted());
491
492 // Make sure this isn't an uncacheable access
493 // A bit of a hackish way to get uncached accesses to work only if they're
494 // at the head of the LSQ and are ready to commit (at the head of the ROB
495 // too).
496 if (req->isUncacheable() &&
497 (load_idx != loadHead || !load_inst->isAtCommit())) {
498 iewStage->rescheduleMemInst(load_inst);
499 ++lsqRescheduledLoads;
500
501 // Must delete request now that it wasn't handed off to
502 // memory. This is quite ugly. @todo: Figure out the proper
503 // place to really handle request deletes.
504 delete req;
505 return TheISA::genMachineCheckFault();
506 }
507
508 // Check the SQ for any previous stores that might lead to forwarding
509 int store_idx = load_inst->sqIdx;
510
511 int store_size = 0;
512
513 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
514 "storeHead: %i addr: %#x\n",
515 load_idx, store_idx, storeHead, req->getPaddr());
516
517 if (req->isLocked()) {
518 // Disable recording the result temporarily. Writing to misc
519 // regs normally updates the result, but this is not the
520 // desired behavior when handling store conditionals.
521 load_inst->recordResult = false;
522 TheISA::handleLockedRead(load_inst.get(), req);
523 load_inst->recordResult = true;
524 }
525
526 while (store_idx != -1) {
527 // End once we've reached the top of the LSQ
528 if (store_idx == storeWBIdx) {
529 break;
530 }
531
532 // Move the index to one younger
533 if (--store_idx < 0)
534 store_idx += SQEntries;
535
536 assert(storeQueue[store_idx].inst);
537
538 store_size = storeQueue[store_idx].size;
539
540 if (store_size == 0)
541 continue;
542 else if (storeQueue[store_idx].inst->uncacheable())
543 continue;
544
545 assert(storeQueue[store_idx].inst->effAddrValid);
546
547 // Check if the store data is within the lower and upper bounds of
548 // addresses that the request needs.
549 bool store_has_lower_limit =
550 req->getVaddr() >= storeQueue[store_idx].inst->effAddr;
551 bool store_has_upper_limit =
552 (req->getVaddr() + req->getSize()) <=
553 (storeQueue[store_idx].inst->effAddr + store_size);
554 bool lower_load_has_store_part =
555 req->getVaddr() < (storeQueue[store_idx].inst->effAddr +
556 store_size);
557 bool upper_load_has_store_part =
558 (req->getVaddr() + req->getSize()) >
559 storeQueue[store_idx].inst->effAddr;
560
561 // If the store's data has all of the data needed, we can forward.
562 if ((store_has_lower_limit && store_has_upper_limit)) {
563 // Get shift amount for offset into the store's data.
564 int shift_amt = req->getVaddr() & (store_size - 1);
| 322 /** Whether or not the store can writeback. */
323 bool canWB;
324 /** Whether or not the store is committed. */
325 bool committed;
326 /** Whether or not the store is completed. */
327 bool completed;
328 };
329
330 private:
331 /** The LSQUnit thread id. */
332 unsigned lsqID;
333
334 /** The store queue. */
335 std::vector<SQEntry> storeQueue;
336
337 /** The load queue. */
338 std::vector<DynInstPtr> loadQueue;
339
340 /** The number of LQ entries, plus a sentinel entry (circular queue).
341 * @todo: Consider having var that records the true number of LQ entries.
342 */
343 unsigned LQEntries;
344 /** The number of SQ entries, plus a sentinel entry (circular queue).
345 * @todo: Consider having var that records the true number of SQ entries.
346 */
347 unsigned SQEntries;
348
349 /** The number of load instructions in the LQ. */
350 int loads;
351 /** The number of store instructions in the SQ. */
352 int stores;
353 /** The number of store instructions in the SQ waiting to writeback. */
354 int storesToWB;
355
356 /** The index of the head instruction in the LQ. */
357 int loadHead;
358 /** The index of the tail instruction in the LQ. */
359 int loadTail;
360
361 /** The index of the head instruction in the SQ. */
362 int storeHead;
363 /** The index of the first instruction that may be ready to be
364 * written back, and has not yet been written back.
365 */
366 int storeWBIdx;
367 /** The index of the tail instruction in the SQ. */
368 int storeTail;
369
370 /// @todo Consider moving to a more advanced model with write vs read ports
371 /** The number of cache ports available each cycle. */
372 int cachePorts;
373
374 /** The number of used cache ports in this cycle. */
375 int usedPorts;
376
377 /** Is the LSQ switched out. */
378 bool switchedOut;
379
380 //list<InstSeqNum> mshrSeqNums;
381
382 /** Wire to read information from the issue stage time queue. */
383 typename TimeBuffer<IssueStruct>::wire fromIssue;
384
385 /** Whether or not the LSQ is stalled. */
386 bool stalled;
387 /** The store that causes the stall due to partial store to load
388 * forwarding.
389 */
390 InstSeqNum stallingStoreIsn;
391 /** The index of the above store. */
392 int stallingLoadIdx;
393
394 /** The packet that needs to be retried. */
395 PacketPtr retryPkt;
396
397 /** Whehter or not a store is blocked due to the memory system. */
398 bool isStoreBlocked;
399
400 /** Whether or not a load is blocked due to the memory system. */
401 bool isLoadBlocked;
402
403 /** Has the blocked load been handled. */
404 bool loadBlockedHandled;
405
406 /** The sequence number of the blocked load. */
407 InstSeqNum blockedLoadSeqNum;
408
409 /** The oldest load that caused a memory ordering violation. */
410 DynInstPtr memDepViolator;
411
412 // Will also need how many read/write ports the Dcache has. Or keep track
413 // of that in stage that is one level up, and only call executeLoad/Store
414 // the appropriate number of times.
415 /** Total number of loads forwaded from LSQ stores. */
416 Stats::Scalar<> lsqForwLoads;
417
418 /** Total number of loads ignored due to invalid addresses. */
419 Stats::Scalar<> invAddrLoads;
420
421 /** Total number of squashed loads. */
422 Stats::Scalar<> lsqSquashedLoads;
423
424 /** Total number of responses from the memory system that are
425 * ignored due to the instruction already being squashed. */
426 Stats::Scalar<> lsqIgnoredResponses;
427
428 /** Tota number of memory ordering violations. */
429 Stats::Scalar<> lsqMemOrderViolation;
430
431 /** Total number of squashed stores. */
432 Stats::Scalar<> lsqSquashedStores;
433
434 /** Total number of software prefetches ignored due to invalid addresses. */
435 Stats::Scalar<> invAddrSwpfs;
436
437 /** Ready loads blocked due to partial store-forwarding. */
438 Stats::Scalar<> lsqBlockedLoads;
439
440 /** Number of loads that were rescheduled. */
441 Stats::Scalar<> lsqRescheduledLoads;
442
443 /** Number of times the LSQ is blocked due to the cache. */
444 Stats::Scalar<> lsqCacheBlocked;
445
446 public:
447 /** Executes the load at the given index. */
448 template <class T>
449 Fault read(Request *req, T &data, int load_idx);
450
451 /** Executes the store at the given index. */
452 template <class T>
453 Fault write(Request *req, T &data, int store_idx);
454
455 /** Returns the index of the head load instruction. */
456 int getLoadHead() { return loadHead; }
457 /** Returns the sequence number of the head load instruction. */
458 InstSeqNum getLoadHeadSeqNum()
459 {
460 if (loadQueue[loadHead]) {
461 return loadQueue[loadHead]->seqNum;
462 } else {
463 return 0;
464 }
465
466 }
467
468 /** Returns the index of the head store instruction. */
469 int getStoreHead() { return storeHead; }
470 /** Returns the sequence number of the head store instruction. */
471 InstSeqNum getStoreHeadSeqNum()
472 {
473 if (storeQueue[storeHead].inst) {
474 return storeQueue[storeHead].inst->seqNum;
475 } else {
476 return 0;
477 }
478
479 }
480
481 /** Returns whether or not the LSQ unit is stalled. */
482 bool isStalled() { return stalled; }
483};
484
485template <class Impl>
486template <class T>
487Fault
488LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
489{
490 DynInstPtr load_inst = loadQueue[load_idx];
491
492 assert(load_inst);
493
494 assert(!load_inst->isExecuted());
495
496 // Make sure this isn't an uncacheable access
497 // A bit of a hackish way to get uncached accesses to work only if they're
498 // at the head of the LSQ and are ready to commit (at the head of the ROB
499 // too).
500 if (req->isUncacheable() &&
501 (load_idx != loadHead || !load_inst->isAtCommit())) {
502 iewStage->rescheduleMemInst(load_inst);
503 ++lsqRescheduledLoads;
504
505 // Must delete request now that it wasn't handed off to
506 // memory. This is quite ugly. @todo: Figure out the proper
507 // place to really handle request deletes.
508 delete req;
509 return TheISA::genMachineCheckFault();
510 }
511
512 // Check the SQ for any previous stores that might lead to forwarding
513 int store_idx = load_inst->sqIdx;
514
515 int store_size = 0;
516
517 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
518 "storeHead: %i addr: %#x\n",
519 load_idx, store_idx, storeHead, req->getPaddr());
520
521 if (req->isLocked()) {
522 // Disable recording the result temporarily. Writing to misc
523 // regs normally updates the result, but this is not the
524 // desired behavior when handling store conditionals.
525 load_inst->recordResult = false;
526 TheISA::handleLockedRead(load_inst.get(), req);
527 load_inst->recordResult = true;
528 }
529
530 while (store_idx != -1) {
531 // End once we've reached the top of the LSQ
532 if (store_idx == storeWBIdx) {
533 break;
534 }
535
536 // Move the index to one younger
537 if (--store_idx < 0)
538 store_idx += SQEntries;
539
540 assert(storeQueue[store_idx].inst);
541
542 store_size = storeQueue[store_idx].size;
543
544 if (store_size == 0)
545 continue;
546 else if (storeQueue[store_idx].inst->uncacheable())
547 continue;
548
549 assert(storeQueue[store_idx].inst->effAddrValid);
550
551 // Check if the store data is within the lower and upper bounds of
552 // addresses that the request needs.
553 bool store_has_lower_limit =
554 req->getVaddr() >= storeQueue[store_idx].inst->effAddr;
555 bool store_has_upper_limit =
556 (req->getVaddr() + req->getSize()) <=
557 (storeQueue[store_idx].inst->effAddr + store_size);
558 bool lower_load_has_store_part =
559 req->getVaddr() < (storeQueue[store_idx].inst->effAddr +
560 store_size);
561 bool upper_load_has_store_part =
562 (req->getVaddr() + req->getSize()) >
563 storeQueue[store_idx].inst->effAddr;
564
565 // If the store's data has all of the data needed, we can forward.
566 if ((store_has_lower_limit && store_has_upper_limit)) {
567 // Get shift amount for offset into the store's data.
568 int shift_amt = req->getVaddr() & (store_size - 1);
|
565 // @todo: Magic number, assumes byte addressing
566 shift_amt = shift_amt << 3;
| |
567
| 569
|
568 // Cast this to type T?
569 data = storeQueue[store_idx].data >> shift_amt;
| 570 memcpy(&data, storeQueue[store_idx].data + shift_amt, sizeof(T));
|
570
| 571
|
571 // When the data comes from the store queue entry, it's in host
572 // order. When it gets sent to the load, it needs to be in guest
573 // order so when the load converts it again, it ends up back
574 // in host order like the inst expects.
575 data = TheISA::htog(data);
576
| |
577 assert(!load_inst->memData);
578 load_inst->memData = new uint8_t[64];
579
| 572 assert(!load_inst->memData);
573 load_inst->memData = new uint8_t[64];
574
|
580 memcpy(load_inst->memData, &data, req->getSize());
| 575 memcpy(load_inst->memData,
576 storeQueue[store_idx].data + shift_amt, req->getSize());
|
581
582 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
583 "addr %#x, data %#x\n",
584 store_idx, req->getVaddr(), data);
585
586 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq,
587 Packet::Broadcast);
588 data_pkt->dataStatic(load_inst->memData);
589
590 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
591
592 // We'll say this has a 1 cycle load-store forwarding latency
593 // for now.
594 // @todo: Need to make this a parameter.
595 wb->schedule(curTick);
596
597 ++lsqForwLoads;
598 return NoFault;
599 } else if ((store_has_lower_limit && lower_load_has_store_part) ||
600 (store_has_upper_limit && upper_load_has_store_part) ||
601 (lower_load_has_store_part && upper_load_has_store_part)) {
602 // This is the partial store-load forwarding case where a store
603 // has only part of the load's data.
604
605 // If it's already been written back, then don't worry about
606 // stalling on it.
607 if (storeQueue[store_idx].completed) {
608 panic("Should not check one of these");
609 continue;
610 }
611
612 // Must stall load and force it to retry, so long as it's the oldest
613 // load that needs to do so.
614 if (!stalled ||
615 (stalled &&
616 load_inst->seqNum <
617 loadQueue[stallingLoadIdx]->seqNum)) {
618 stalled = true;
619 stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
620 stallingLoadIdx = load_idx;
621 }
622
623 // Tell IQ/mem dep unit that this instruction will need to be
624 // rescheduled eventually
625 iewStage->rescheduleMemInst(load_inst);
626 iewStage->decrWb(load_inst->seqNum);
627 load_inst->clearIssued();
628 ++lsqRescheduledLoads;
629
630 // Do not generate a writeback event as this instruction is not
631 // complete.
632 DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
633 "Store idx %i to load addr %#x\n",
634 store_idx, req->getVaddr());
635
636 // Must delete request now that it wasn't handed off to
637 // memory. This is quite ugly. @todo: Figure out the
638 // proper place to really handle request deletes.
639 delete req;
640
641 return NoFault;
642 }
643 }
644
645 // If there's no forwarding case, then go access memory
646 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %#x\n",
647 load_inst->seqNum, load_inst->readPC());
648
649 assert(!load_inst->memData);
650 load_inst->memData = new uint8_t[64];
651
652 ++usedPorts;
653
654 // if we the cache is not blocked, do cache access
655 if (!lsq->cacheBlocked()) {
656 PacketPtr data_pkt =
657 new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
658 data_pkt->dataStatic(load_inst->memData);
659
660 LSQSenderState *state = new LSQSenderState;
661 state->isLoad = true;
662 state->idx = load_idx;
663 state->inst = load_inst;
664 data_pkt->senderState = state;
665
666 if (!dcachePort->sendTiming(data_pkt)) {
667 Packet::Result result = data_pkt->result;
668
669 // Delete state and data packet because a load retry
670 // initiates a pipeline restart; it does not retry.
671 delete state;
672 delete data_pkt->req;
673 delete data_pkt;
674
675 req = NULL;
676
677 if (result == Packet::BadAddress) {
678 return TheISA::genMachineCheckFault();
679 }
680
681 // If the access didn't succeed, tell the LSQ by setting
682 // the retry thread id.
683 lsq->setRetryTid(lsqID);
684 }
685 }
686
687 // If the cache was blocked, or has become blocked due to the access,
688 // handle it.
689 if (lsq->cacheBlocked()) {
690 if (req)
691 delete req;
692
693 ++lsqCacheBlocked;
694
695 iewStage->decrWb(load_inst->seqNum);
696 // There's an older load that's already going to squash.
697 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
698 return NoFault;
699
700 // Record that the load was blocked due to memory. This
701 // load will squash all instructions after it, be
702 // refetched, and re-executed.
703 isLoadBlocked = true;
704 loadBlockedHandled = false;
705 blockedLoadSeqNum = load_inst->seqNum;
706 // No fault occurred, even though the interface is blocked.
707 return NoFault;
708 }
709
710 return NoFault;
711}
712
713template <class Impl>
714template <class T>
715Fault
716LSQUnit<Impl>::write(Request *req, T &data, int store_idx)
717{
718 assert(storeQueue[store_idx].inst);
719
720 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x"
721 " | storeHead:%i [sn:%i]\n",
722 store_idx, req->getPaddr(), data, storeHead,
723 storeQueue[store_idx].inst->seqNum);
724
725 storeQueue[store_idx].req = req;
726 storeQueue[store_idx].size = sizeof(T);
| 577
578 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
579 "addr %#x, data %#x\n",
580 store_idx, req->getVaddr(), data);
581
582 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq,
583 Packet::Broadcast);
584 data_pkt->dataStatic(load_inst->memData);
585
586 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
587
588 // We'll say this has a 1 cycle load-store forwarding latency
589 // for now.
590 // @todo: Need to make this a parameter.
591 wb->schedule(curTick);
592
593 ++lsqForwLoads;
594 return NoFault;
595 } else if ((store_has_lower_limit && lower_load_has_store_part) ||
596 (store_has_upper_limit && upper_load_has_store_part) ||
597 (lower_load_has_store_part && upper_load_has_store_part)) {
598 // This is the partial store-load forwarding case where a store
599 // has only part of the load's data.
600
601 // If it's already been written back, then don't worry about
602 // stalling on it.
603 if (storeQueue[store_idx].completed) {
604 panic("Should not check one of these");
605 continue;
606 }
607
608 // Must stall load and force it to retry, so long as it's the oldest
609 // load that needs to do so.
610 if (!stalled ||
611 (stalled &&
612 load_inst->seqNum <
613 loadQueue[stallingLoadIdx]->seqNum)) {
614 stalled = true;
615 stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
616 stallingLoadIdx = load_idx;
617 }
618
619 // Tell IQ/mem dep unit that this instruction will need to be
620 // rescheduled eventually
621 iewStage->rescheduleMemInst(load_inst);
622 iewStage->decrWb(load_inst->seqNum);
623 load_inst->clearIssued();
624 ++lsqRescheduledLoads;
625
626 // Do not generate a writeback event as this instruction is not
627 // complete.
628 DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
629 "Store idx %i to load addr %#x\n",
630 store_idx, req->getVaddr());
631
632 // Must delete request now that it wasn't handed off to
633 // memory. This is quite ugly. @todo: Figure out the
634 // proper place to really handle request deletes.
635 delete req;
636
637 return NoFault;
638 }
639 }
640
641 // If there's no forwarding case, then go access memory
642 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %#x\n",
643 load_inst->seqNum, load_inst->readPC());
644
645 assert(!load_inst->memData);
646 load_inst->memData = new uint8_t[64];
647
648 ++usedPorts;
649
650 // if we the cache is not blocked, do cache access
651 if (!lsq->cacheBlocked()) {
652 PacketPtr data_pkt =
653 new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
654 data_pkt->dataStatic(load_inst->memData);
655
656 LSQSenderState *state = new LSQSenderState;
657 state->isLoad = true;
658 state->idx = load_idx;
659 state->inst = load_inst;
660 data_pkt->senderState = state;
661
662 if (!dcachePort->sendTiming(data_pkt)) {
663 Packet::Result result = data_pkt->result;
664
665 // Delete state and data packet because a load retry
666 // initiates a pipeline restart; it does not retry.
667 delete state;
668 delete data_pkt->req;
669 delete data_pkt;
670
671 req = NULL;
672
673 if (result == Packet::BadAddress) {
674 return TheISA::genMachineCheckFault();
675 }
676
677 // If the access didn't succeed, tell the LSQ by setting
678 // the retry thread id.
679 lsq->setRetryTid(lsqID);
680 }
681 }
682
683 // If the cache was blocked, or has become blocked due to the access,
684 // handle it.
685 if (lsq->cacheBlocked()) {
686 if (req)
687 delete req;
688
689 ++lsqCacheBlocked;
690
691 iewStage->decrWb(load_inst->seqNum);
692 // There's an older load that's already going to squash.
693 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
694 return NoFault;
695
696 // Record that the load was blocked due to memory. This
697 // load will squash all instructions after it, be
698 // refetched, and re-executed.
699 isLoadBlocked = true;
700 loadBlockedHandled = false;
701 blockedLoadSeqNum = load_inst->seqNum;
702 // No fault occurred, even though the interface is blocked.
703 return NoFault;
704 }
705
706 return NoFault;
707}
708
709template <class Impl>
710template <class T>
711Fault
712LSQUnit<Impl>::write(Request *req, T &data, int store_idx)
713{
714 assert(storeQueue[store_idx].inst);
715
716 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x"
717 " | storeHead:%i [sn:%i]\n",
718 store_idx, req->getPaddr(), data, storeHead,
719 storeQueue[store_idx].inst->seqNum);
720
721 storeQueue[store_idx].req = req;
722 storeQueue[store_idx].size = sizeof(T);
|
727 storeQueue[store_idx].data = data;
| 723 assert(sizeof(T) <= sizeof(storeQueue[store_idx].data));
|
728
| 724
|
| 725 T gData = htog(data);
726 memcpy(storeQueue[store_idx].data, &gData, sizeof(T));
727
|
729 // This function only writes the data to the store queue, so no fault
730 // can happen here.
731 return NoFault;
732}
733
734#endif // __CPU_O3_LSQ_UNIT_HH__
| 728 // This function only writes the data to the store queue, so no fault
729 // can happen here.
730 return NoFault;
731}
732
733#endif // __CPU_O3_LSQ_UNIT_HH__
|