1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_LSQ_UNIT_HH__ 33#define __CPU_O3_LSQ_UNIT_HH__ 34 35#include <algorithm> 36#include <map> 37#include <queue> 38 39#include "arch/faults.hh"
| 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_LSQ_UNIT_HH__ 33#define __CPU_O3_LSQ_UNIT_HH__ 34 35#include <algorithm> 36#include <map> 37#include <queue> 38 39#include "arch/faults.hh"
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| 40#include "arch/locked_mem.hh"
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40#include "config/full_system.hh" 41#include "base/hashmap.hh" 42#include "cpu/inst_seq.hh" 43#include "mem/packet.hh" 44#include "mem/port.hh" 45 46/** 47 * Class that implements the actual LQ and SQ for each specific 48 * thread. Both are circular queues; load entries are freed upon 49 * committing, while store entries are freed once they writeback. The 50 * LSQUnit tracks if there are memory ordering violations, and also 51 * detects partial load to store forwarding cases (a store only has 52 * part of a load's data) that requires the load to wait until the 53 * store writes back. In the former case it holds onto the instruction 54 * until the dependence unit looks at it, and in the latter it stalls 55 * the LSQ until the store writes back. At that point the load is 56 * replayed. 57 */ 58template <class Impl> 59class LSQUnit { 60 protected: 61 typedef TheISA::IntReg IntReg; 62 public: 63 typedef typename Impl::Params Params; 64 typedef typename Impl::O3CPU O3CPU; 65 typedef typename Impl::DynInstPtr DynInstPtr; 66 typedef typename Impl::CPUPol::IEW IEW; 67 typedef typename Impl::CPUPol::LSQ LSQ; 68 typedef typename Impl::CPUPol::IssueStruct IssueStruct; 69 70 public: 71 /** Constructs an LSQ unit. init() must be called prior to use. */ 72 LSQUnit(); 73 74 /** Initializes the LSQ unit with the specified number of entries. */ 75 void init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries, 76 unsigned maxSQEntries, unsigned id); 77 78 /** Returns the name of the LSQ unit. */ 79 std::string name() const; 80 81 /** Registers statistics. */ 82 void regStats(); 83 84 /** Sets the CPU pointer. */ 85 void setCPU(O3CPU *cpu_ptr); 86 87 /** Sets the IEW stage pointer. */ 88 void setIEW(IEW *iew_ptr) 89 { iewStage = iew_ptr; } 90 91 /** Sets the pointer to the dcache port. */ 92 void setDcachePort(Port *dcache_port) 93 { dcachePort = dcache_port; } 94 95 /** Switches out LSQ unit. */ 96 void switchOut(); 97 98 /** Takes over from another CPU's thread. */ 99 void takeOverFrom(); 100 101 /** Returns if the LSQ is switched out. */ 102 bool isSwitchedOut() { return switchedOut; } 103 104 /** Ticks the LSQ unit, which in this case only resets the number of 105 * used cache ports. 106 * @todo: Move the number of used ports up to the LSQ level so it can 107 * be shared by all LSQ units. 108 */ 109 void tick() { usedPorts = 0; } 110 111 /** Inserts an instruction. */ 112 void insert(DynInstPtr &inst); 113 /** Inserts a load instruction. */ 114 void insertLoad(DynInstPtr &load_inst); 115 /** Inserts a store instruction. */ 116 void insertStore(DynInstPtr &store_inst); 117 118 /** Executes a load instruction. */ 119 Fault executeLoad(DynInstPtr &inst); 120 121 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; } 122 /** Executes a store instruction. */ 123 Fault executeStore(DynInstPtr &inst); 124 125 /** Commits the head load. */ 126 void commitLoad(); 127 /** Commits loads older than a specific sequence number. */ 128 void commitLoads(InstSeqNum &youngest_inst); 129 130 /** Commits stores older than a specific sequence number. */ 131 void commitStores(InstSeqNum &youngest_inst); 132 133 /** Writes back stores. */ 134 void writebackStores(); 135 136 /** Completes the data access that has been returned from the 137 * memory system. */ 138 void completeDataAccess(PacketPtr pkt); 139 140 /** Clears all the entries in the LQ. */ 141 void clearLQ(); 142 143 /** Clears all the entries in the SQ. */ 144 void clearSQ(); 145 146 /** Resizes the LQ to a given size. */ 147 void resizeLQ(unsigned size); 148 149 /** Resizes the SQ to a given size. */ 150 void resizeSQ(unsigned size); 151 152 /** Squashes all instructions younger than a specific sequence number. */ 153 void squash(const InstSeqNum &squashed_num); 154 155 /** Returns if there is a memory ordering violation. Value is reset upon 156 * call to getMemDepViolator(). 157 */ 158 bool violation() { return memDepViolator; } 159 160 /** Returns the memory ordering violator. */ 161 DynInstPtr getMemDepViolator(); 162 163 /** Returns if a load became blocked due to the memory system. */ 164 bool loadBlocked() 165 { return isLoadBlocked; } 166 167 /** Clears the signal that a load became blocked. */ 168 void clearLoadBlocked() 169 { isLoadBlocked = false; } 170 171 /** Returns if the blocked load was handled. */ 172 bool isLoadBlockedHandled() 173 { return loadBlockedHandled; } 174 175 /** Records the blocked load as being handled. */ 176 void setLoadBlockedHandled() 177 { loadBlockedHandled = true; } 178 179 /** Returns the number of free entries (min of free LQ and SQ entries). */ 180 unsigned numFreeEntries(); 181 182 /** Returns the number of loads ready to execute. */ 183 int numLoadsReady(); 184 185 /** Returns the number of loads in the LQ. */ 186 int numLoads() { return loads; } 187 188 /** Returns the number of stores in the SQ. */ 189 int numStores() { return stores; } 190 191 /** Returns if either the LQ or SQ is full. */ 192 bool isFull() { return lqFull() || sqFull(); } 193 194 /** Returns if the LQ is full. */ 195 bool lqFull() { return loads >= (LQEntries - 1); } 196 197 /** Returns if the SQ is full. */ 198 bool sqFull() { return stores >= (SQEntries - 1); } 199 200 /** Returns the number of instructions in the LSQ. */ 201 unsigned getCount() { return loads + stores; } 202 203 /** Returns if there are any stores to writeback. */ 204 bool hasStoresToWB() { return storesToWB; } 205 206 /** Returns the number of stores to writeback. */ 207 int numStoresToWB() { return storesToWB; } 208 209 /** Returns if the LSQ unit will writeback on this cycle. */ 210 bool willWB() { return storeQueue[storeWBIdx].canWB && 211 !storeQueue[storeWBIdx].completed && 212 !isStoreBlocked; } 213 214 /** Handles doing the retry. */ 215 void recvRetry(); 216 217 private: 218 /** Writes back the instruction, sending it to IEW. */ 219 void writeback(DynInstPtr &inst, PacketPtr pkt); 220 221 /** Handles completing the send of a store to memory. */ 222 void storePostSend(PacketPtr pkt); 223 224 /** Completes the store at the specified index. */ 225 void completeStore(int store_idx); 226 227 /** Increments the given store index (circular queue). */ 228 inline void incrStIdx(int &store_idx); 229 /** Decrements the given store index (circular queue). */ 230 inline void decrStIdx(int &store_idx); 231 /** Increments the given load index (circular queue). */ 232 inline void incrLdIdx(int &load_idx); 233 /** Decrements the given load index (circular queue). */ 234 inline void decrLdIdx(int &load_idx); 235 236 public: 237 /** Debugging function to dump instructions in the LSQ. */ 238 void dumpInsts(); 239 240 private: 241 /** Pointer to the CPU. */ 242 O3CPU *cpu; 243 244 /** Pointer to the IEW stage. */ 245 IEW *iewStage; 246 247 /** Pointer to the LSQ. */ 248 LSQ *lsq; 249 250 /** Pointer to the dcache port. Used only for sending. */ 251 Port *dcachePort; 252 253 /** Derived class to hold any sender state the LSQ needs. */ 254 class LSQSenderState : public Packet::SenderState 255 { 256 public: 257 /** Default constructor. */ 258 LSQSenderState() 259 : noWB(false) 260 { } 261 262 /** Instruction who initiated the access to memory. */ 263 DynInstPtr inst; 264 /** Whether or not it is a load. */ 265 bool isLoad; 266 /** The LQ/SQ index of the instruction. */ 267 int idx; 268 /** Whether or not the instruction will need to writeback. */ 269 bool noWB; 270 }; 271 272 /** Writeback event, specifically for when stores forward data to loads. */ 273 class WritebackEvent : public Event { 274 public: 275 /** Constructs a writeback event. */ 276 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr); 277 278 /** Processes the writeback event. */ 279 void process(); 280 281 /** Returns the description of this event. */ 282 const char *description(); 283 284 private: 285 /** Instruction whose results are being written back. */ 286 DynInstPtr inst; 287 288 /** The packet that would have been sent to memory. */ 289 PacketPtr pkt; 290 291 /** The pointer to the LSQ unit that issued the store. */ 292 LSQUnit<Impl> *lsqPtr; 293 }; 294 295 public: 296 struct SQEntry { 297 /** Constructs an empty store queue entry. */ 298 SQEntry() 299 : inst(NULL), req(NULL), size(0), data(0), 300 canWB(0), committed(0), completed(0) 301 { } 302 303 /** Constructs a store queue entry for a given instruction. */ 304 SQEntry(DynInstPtr &_inst) 305 : inst(_inst), req(NULL), size(0), data(0), 306 canWB(0), committed(0), completed(0) 307 { } 308 309 /** The store instruction. */ 310 DynInstPtr inst; 311 /** The request for the store. */ 312 RequestPtr req; 313 /** The size of the store. */ 314 int size; 315 /** The store data. */ 316 IntReg data; 317 /** Whether or not the store can writeback. */ 318 bool canWB; 319 /** Whether or not the store is committed. */ 320 bool committed; 321 /** Whether or not the store is completed. */ 322 bool completed; 323 }; 324 325 private: 326 /** The LSQUnit thread id. */ 327 unsigned lsqID; 328 329 /** The store queue. */ 330 std::vector<SQEntry> storeQueue; 331 332 /** The load queue. */ 333 std::vector<DynInstPtr> loadQueue; 334 335 /** The number of LQ entries, plus a sentinel entry (circular queue). 336 * @todo: Consider having var that records the true number of LQ entries. 337 */ 338 unsigned LQEntries; 339 /** The number of SQ entries, plus a sentinel entry (circular queue). 340 * @todo: Consider having var that records the true number of SQ entries. 341 */ 342 unsigned SQEntries; 343 344 /** The number of load instructions in the LQ. */ 345 int loads; 346 /** The number of store instructions in the SQ. */ 347 int stores; 348 /** The number of store instructions in the SQ waiting to writeback. */ 349 int storesToWB; 350 351 /** The index of the head instruction in the LQ. */ 352 int loadHead; 353 /** The index of the tail instruction in the LQ. */ 354 int loadTail; 355 356 /** The index of the head instruction in the SQ. */ 357 int storeHead; 358 /** The index of the first instruction that may be ready to be 359 * written back, and has not yet been written back. 360 */ 361 int storeWBIdx; 362 /** The index of the tail instruction in the SQ. */ 363 int storeTail; 364 365 /// @todo Consider moving to a more advanced model with write vs read ports 366 /** The number of cache ports available each cycle. */ 367 int cachePorts; 368 369 /** The number of used cache ports in this cycle. */ 370 int usedPorts; 371 372 /** Is the LSQ switched out. */ 373 bool switchedOut; 374 375 //list<InstSeqNum> mshrSeqNums; 376 377 /** Wire to read information from the issue stage time queue. */ 378 typename TimeBuffer<IssueStruct>::wire fromIssue; 379 380 /** Whether or not the LSQ is stalled. */ 381 bool stalled; 382 /** The store that causes the stall due to partial store to load 383 * forwarding. 384 */ 385 InstSeqNum stallingStoreIsn; 386 /** The index of the above store. */ 387 int stallingLoadIdx; 388 389 /** The packet that needs to be retried. */ 390 PacketPtr retryPkt; 391 392 /** Whehter or not a store is blocked due to the memory system. */ 393 bool isStoreBlocked; 394 395 /** Whether or not a load is blocked due to the memory system. */ 396 bool isLoadBlocked; 397 398 /** Has the blocked load been handled. */ 399 bool loadBlockedHandled; 400 401 /** The sequence number of the blocked load. */ 402 InstSeqNum blockedLoadSeqNum; 403 404 /** The oldest load that caused a memory ordering violation. */ 405 DynInstPtr memDepViolator; 406 407 // Will also need how many read/write ports the Dcache has. Or keep track 408 // of that in stage that is one level up, and only call executeLoad/Store 409 // the appropriate number of times. 410 /** Total number of loads forwaded from LSQ stores. */ 411 Stats::Scalar<> lsqForwLoads; 412 413 /** Total number of loads ignored due to invalid addresses. */ 414 Stats::Scalar<> invAddrLoads; 415 416 /** Total number of squashed loads. */ 417 Stats::Scalar<> lsqSquashedLoads; 418 419 /** Total number of responses from the memory system that are 420 * ignored due to the instruction already being squashed. */ 421 Stats::Scalar<> lsqIgnoredResponses; 422 423 /** Tota number of memory ordering violations. */ 424 Stats::Scalar<> lsqMemOrderViolation; 425 426 /** Total number of squashed stores. */ 427 Stats::Scalar<> lsqSquashedStores; 428 429 /** Total number of software prefetches ignored due to invalid addresses. */ 430 Stats::Scalar<> invAddrSwpfs; 431 432 /** Ready loads blocked due to partial store-forwarding. */ 433 Stats::Scalar<> lsqBlockedLoads; 434 435 /** Number of loads that were rescheduled. */ 436 Stats::Scalar<> lsqRescheduledLoads; 437 438 /** Number of times the LSQ is blocked due to the cache. */ 439 Stats::Scalar<> lsqCacheBlocked; 440 441 public: 442 /** Executes the load at the given index. */ 443 template <class T> 444 Fault read(Request *req, T &data, int load_idx); 445 446 /** Executes the store at the given index. */ 447 template <class T> 448 Fault write(Request *req, T &data, int store_idx); 449 450 /** Returns the index of the head load instruction. */ 451 int getLoadHead() { return loadHead; } 452 /** Returns the sequence number of the head load instruction. */ 453 InstSeqNum getLoadHeadSeqNum() 454 { 455 if (loadQueue[loadHead]) { 456 return loadQueue[loadHead]->seqNum; 457 } else { 458 return 0; 459 } 460 461 } 462 463 /** Returns the index of the head store instruction. */ 464 int getStoreHead() { return storeHead; } 465 /** Returns the sequence number of the head store instruction. */ 466 InstSeqNum getStoreHeadSeqNum() 467 { 468 if (storeQueue[storeHead].inst) { 469 return storeQueue[storeHead].inst->seqNum; 470 } else { 471 return 0; 472 } 473 474 } 475 476 /** Returns whether or not the LSQ unit is stalled. */ 477 bool isStalled() { return stalled; } 478}; 479 480template <class Impl> 481template <class T> 482Fault 483LSQUnit<Impl>::read(Request *req, T &data, int load_idx) 484{ 485 DynInstPtr load_inst = loadQueue[load_idx]; 486 487 assert(load_inst); 488 489 assert(!load_inst->isExecuted()); 490 491 // Make sure this isn't an uncacheable access 492 // A bit of a hackish way to get uncached accesses to work only if they're 493 // at the head of the LSQ and are ready to commit (at the head of the ROB 494 // too). 495 if (req->isUncacheable() && 496 (load_idx != loadHead || !load_inst->isAtCommit())) { 497 iewStage->rescheduleMemInst(load_inst); 498 ++lsqRescheduledLoads; 499 return TheISA::genMachineCheckFault(); 500 } 501 502 // Check the SQ for any previous stores that might lead to forwarding 503 int store_idx = load_inst->sqIdx; 504 505 int store_size = 0; 506 507 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, " 508 "storeHead: %i addr: %#x\n", 509 load_idx, store_idx, storeHead, req->getPaddr()); 510 511#if FULL_SYSTEM 512 if (req->isLocked()) {
| 41#include "config/full_system.hh" 42#include "base/hashmap.hh" 43#include "cpu/inst_seq.hh" 44#include "mem/packet.hh" 45#include "mem/port.hh" 46 47/** 48 * Class that implements the actual LQ and SQ for each specific 49 * thread. Both are circular queues; load entries are freed upon 50 * committing, while store entries are freed once they writeback. The 51 * LSQUnit tracks if there are memory ordering violations, and also 52 * detects partial load to store forwarding cases (a store only has 53 * part of a load's data) that requires the load to wait until the 54 * store writes back. In the former case it holds onto the instruction 55 * until the dependence unit looks at it, and in the latter it stalls 56 * the LSQ until the store writes back. At that point the load is 57 * replayed. 58 */ 59template <class Impl> 60class LSQUnit { 61 protected: 62 typedef TheISA::IntReg IntReg; 63 public: 64 typedef typename Impl::Params Params; 65 typedef typename Impl::O3CPU O3CPU; 66 typedef typename Impl::DynInstPtr DynInstPtr; 67 typedef typename Impl::CPUPol::IEW IEW; 68 typedef typename Impl::CPUPol::LSQ LSQ; 69 typedef typename Impl::CPUPol::IssueStruct IssueStruct; 70 71 public: 72 /** Constructs an LSQ unit. init() must be called prior to use. */ 73 LSQUnit(); 74 75 /** Initializes the LSQ unit with the specified number of entries. */ 76 void init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries, 77 unsigned maxSQEntries, unsigned id); 78 79 /** Returns the name of the LSQ unit. */ 80 std::string name() const; 81 82 /** Registers statistics. */ 83 void regStats(); 84 85 /** Sets the CPU pointer. */ 86 void setCPU(O3CPU *cpu_ptr); 87 88 /** Sets the IEW stage pointer. */ 89 void setIEW(IEW *iew_ptr) 90 { iewStage = iew_ptr; } 91 92 /** Sets the pointer to the dcache port. */ 93 void setDcachePort(Port *dcache_port) 94 { dcachePort = dcache_port; } 95 96 /** Switches out LSQ unit. */ 97 void switchOut(); 98 99 /** Takes over from another CPU's thread. */ 100 void takeOverFrom(); 101 102 /** Returns if the LSQ is switched out. */ 103 bool isSwitchedOut() { return switchedOut; } 104 105 /** Ticks the LSQ unit, which in this case only resets the number of 106 * used cache ports. 107 * @todo: Move the number of used ports up to the LSQ level so it can 108 * be shared by all LSQ units. 109 */ 110 void tick() { usedPorts = 0; } 111 112 /** Inserts an instruction. */ 113 void insert(DynInstPtr &inst); 114 /** Inserts a load instruction. */ 115 void insertLoad(DynInstPtr &load_inst); 116 /** Inserts a store instruction. */ 117 void insertStore(DynInstPtr &store_inst); 118 119 /** Executes a load instruction. */ 120 Fault executeLoad(DynInstPtr &inst); 121 122 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; } 123 /** Executes a store instruction. */ 124 Fault executeStore(DynInstPtr &inst); 125 126 /** Commits the head load. */ 127 void commitLoad(); 128 /** Commits loads older than a specific sequence number. */ 129 void commitLoads(InstSeqNum &youngest_inst); 130 131 /** Commits stores older than a specific sequence number. */ 132 void commitStores(InstSeqNum &youngest_inst); 133 134 /** Writes back stores. */ 135 void writebackStores(); 136 137 /** Completes the data access that has been returned from the 138 * memory system. */ 139 void completeDataAccess(PacketPtr pkt); 140 141 /** Clears all the entries in the LQ. */ 142 void clearLQ(); 143 144 /** Clears all the entries in the SQ. */ 145 void clearSQ(); 146 147 /** Resizes the LQ to a given size. */ 148 void resizeLQ(unsigned size); 149 150 /** Resizes the SQ to a given size. */ 151 void resizeSQ(unsigned size); 152 153 /** Squashes all instructions younger than a specific sequence number. */ 154 void squash(const InstSeqNum &squashed_num); 155 156 /** Returns if there is a memory ordering violation. Value is reset upon 157 * call to getMemDepViolator(). 158 */ 159 bool violation() { return memDepViolator; } 160 161 /** Returns the memory ordering violator. */ 162 DynInstPtr getMemDepViolator(); 163 164 /** Returns if a load became blocked due to the memory system. */ 165 bool loadBlocked() 166 { return isLoadBlocked; } 167 168 /** Clears the signal that a load became blocked. */ 169 void clearLoadBlocked() 170 { isLoadBlocked = false; } 171 172 /** Returns if the blocked load was handled. */ 173 bool isLoadBlockedHandled() 174 { return loadBlockedHandled; } 175 176 /** Records the blocked load as being handled. */ 177 void setLoadBlockedHandled() 178 { loadBlockedHandled = true; } 179 180 /** Returns the number of free entries (min of free LQ and SQ entries). */ 181 unsigned numFreeEntries(); 182 183 /** Returns the number of loads ready to execute. */ 184 int numLoadsReady(); 185 186 /** Returns the number of loads in the LQ. */ 187 int numLoads() { return loads; } 188 189 /** Returns the number of stores in the SQ. */ 190 int numStores() { return stores; } 191 192 /** Returns if either the LQ or SQ is full. */ 193 bool isFull() { return lqFull() || sqFull(); } 194 195 /** Returns if the LQ is full. */ 196 bool lqFull() { return loads >= (LQEntries - 1); } 197 198 /** Returns if the SQ is full. */ 199 bool sqFull() { return stores >= (SQEntries - 1); } 200 201 /** Returns the number of instructions in the LSQ. */ 202 unsigned getCount() { return loads + stores; } 203 204 /** Returns if there are any stores to writeback. */ 205 bool hasStoresToWB() { return storesToWB; } 206 207 /** Returns the number of stores to writeback. */ 208 int numStoresToWB() { return storesToWB; } 209 210 /** Returns if the LSQ unit will writeback on this cycle. */ 211 bool willWB() { return storeQueue[storeWBIdx].canWB && 212 !storeQueue[storeWBIdx].completed && 213 !isStoreBlocked; } 214 215 /** Handles doing the retry. */ 216 void recvRetry(); 217 218 private: 219 /** Writes back the instruction, sending it to IEW. */ 220 void writeback(DynInstPtr &inst, PacketPtr pkt); 221 222 /** Handles completing the send of a store to memory. */ 223 void storePostSend(PacketPtr pkt); 224 225 /** Completes the store at the specified index. */ 226 void completeStore(int store_idx); 227 228 /** Increments the given store index (circular queue). */ 229 inline void incrStIdx(int &store_idx); 230 /** Decrements the given store index (circular queue). */ 231 inline void decrStIdx(int &store_idx); 232 /** Increments the given load index (circular queue). */ 233 inline void incrLdIdx(int &load_idx); 234 /** Decrements the given load index (circular queue). */ 235 inline void decrLdIdx(int &load_idx); 236 237 public: 238 /** Debugging function to dump instructions in the LSQ. */ 239 void dumpInsts(); 240 241 private: 242 /** Pointer to the CPU. */ 243 O3CPU *cpu; 244 245 /** Pointer to the IEW stage. */ 246 IEW *iewStage; 247 248 /** Pointer to the LSQ. */ 249 LSQ *lsq; 250 251 /** Pointer to the dcache port. Used only for sending. */ 252 Port *dcachePort; 253 254 /** Derived class to hold any sender state the LSQ needs. */ 255 class LSQSenderState : public Packet::SenderState 256 { 257 public: 258 /** Default constructor. */ 259 LSQSenderState() 260 : noWB(false) 261 { } 262 263 /** Instruction who initiated the access to memory. */ 264 DynInstPtr inst; 265 /** Whether or not it is a load. */ 266 bool isLoad; 267 /** The LQ/SQ index of the instruction. */ 268 int idx; 269 /** Whether or not the instruction will need to writeback. */ 270 bool noWB; 271 }; 272 273 /** Writeback event, specifically for when stores forward data to loads. */ 274 class WritebackEvent : public Event { 275 public: 276 /** Constructs a writeback event. */ 277 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr); 278 279 /** Processes the writeback event. */ 280 void process(); 281 282 /** Returns the description of this event. */ 283 const char *description(); 284 285 private: 286 /** Instruction whose results are being written back. */ 287 DynInstPtr inst; 288 289 /** The packet that would have been sent to memory. */ 290 PacketPtr pkt; 291 292 /** The pointer to the LSQ unit that issued the store. */ 293 LSQUnit<Impl> *lsqPtr; 294 }; 295 296 public: 297 struct SQEntry { 298 /** Constructs an empty store queue entry. */ 299 SQEntry() 300 : inst(NULL), req(NULL), size(0), data(0), 301 canWB(0), committed(0), completed(0) 302 { } 303 304 /** Constructs a store queue entry for a given instruction. */ 305 SQEntry(DynInstPtr &_inst) 306 : inst(_inst), req(NULL), size(0), data(0), 307 canWB(0), committed(0), completed(0) 308 { } 309 310 /** The store instruction. */ 311 DynInstPtr inst; 312 /** The request for the store. */ 313 RequestPtr req; 314 /** The size of the store. */ 315 int size; 316 /** The store data. */ 317 IntReg data; 318 /** Whether or not the store can writeback. */ 319 bool canWB; 320 /** Whether or not the store is committed. */ 321 bool committed; 322 /** Whether or not the store is completed. */ 323 bool completed; 324 }; 325 326 private: 327 /** The LSQUnit thread id. */ 328 unsigned lsqID; 329 330 /** The store queue. */ 331 std::vector<SQEntry> storeQueue; 332 333 /** The load queue. */ 334 std::vector<DynInstPtr> loadQueue; 335 336 /** The number of LQ entries, plus a sentinel entry (circular queue). 337 * @todo: Consider having var that records the true number of LQ entries. 338 */ 339 unsigned LQEntries; 340 /** The number of SQ entries, plus a sentinel entry (circular queue). 341 * @todo: Consider having var that records the true number of SQ entries. 342 */ 343 unsigned SQEntries; 344 345 /** The number of load instructions in the LQ. */ 346 int loads; 347 /** The number of store instructions in the SQ. */ 348 int stores; 349 /** The number of store instructions in the SQ waiting to writeback. */ 350 int storesToWB; 351 352 /** The index of the head instruction in the LQ. */ 353 int loadHead; 354 /** The index of the tail instruction in the LQ. */ 355 int loadTail; 356 357 /** The index of the head instruction in the SQ. */ 358 int storeHead; 359 /** The index of the first instruction that may be ready to be 360 * written back, and has not yet been written back. 361 */ 362 int storeWBIdx; 363 /** The index of the tail instruction in the SQ. */ 364 int storeTail; 365 366 /// @todo Consider moving to a more advanced model with write vs read ports 367 /** The number of cache ports available each cycle. */ 368 int cachePorts; 369 370 /** The number of used cache ports in this cycle. */ 371 int usedPorts; 372 373 /** Is the LSQ switched out. */ 374 bool switchedOut; 375 376 //list<InstSeqNum> mshrSeqNums; 377 378 /** Wire to read information from the issue stage time queue. */ 379 typename TimeBuffer<IssueStruct>::wire fromIssue; 380 381 /** Whether or not the LSQ is stalled. */ 382 bool stalled; 383 /** The store that causes the stall due to partial store to load 384 * forwarding. 385 */ 386 InstSeqNum stallingStoreIsn; 387 /** The index of the above store. */ 388 int stallingLoadIdx; 389 390 /** The packet that needs to be retried. */ 391 PacketPtr retryPkt; 392 393 /** Whehter or not a store is blocked due to the memory system. */ 394 bool isStoreBlocked; 395 396 /** Whether or not a load is blocked due to the memory system. */ 397 bool isLoadBlocked; 398 399 /** Has the blocked load been handled. */ 400 bool loadBlockedHandled; 401 402 /** The sequence number of the blocked load. */ 403 InstSeqNum blockedLoadSeqNum; 404 405 /** The oldest load that caused a memory ordering violation. */ 406 DynInstPtr memDepViolator; 407 408 // Will also need how many read/write ports the Dcache has. Or keep track 409 // of that in stage that is one level up, and only call executeLoad/Store 410 // the appropriate number of times. 411 /** Total number of loads forwaded from LSQ stores. */ 412 Stats::Scalar<> lsqForwLoads; 413 414 /** Total number of loads ignored due to invalid addresses. */ 415 Stats::Scalar<> invAddrLoads; 416 417 /** Total number of squashed loads. */ 418 Stats::Scalar<> lsqSquashedLoads; 419 420 /** Total number of responses from the memory system that are 421 * ignored due to the instruction already being squashed. */ 422 Stats::Scalar<> lsqIgnoredResponses; 423 424 /** Tota number of memory ordering violations. */ 425 Stats::Scalar<> lsqMemOrderViolation; 426 427 /** Total number of squashed stores. */ 428 Stats::Scalar<> lsqSquashedStores; 429 430 /** Total number of software prefetches ignored due to invalid addresses. */ 431 Stats::Scalar<> invAddrSwpfs; 432 433 /** Ready loads blocked due to partial store-forwarding. */ 434 Stats::Scalar<> lsqBlockedLoads; 435 436 /** Number of loads that were rescheduled. */ 437 Stats::Scalar<> lsqRescheduledLoads; 438 439 /** Number of times the LSQ is blocked due to the cache. */ 440 Stats::Scalar<> lsqCacheBlocked; 441 442 public: 443 /** Executes the load at the given index. */ 444 template <class T> 445 Fault read(Request *req, T &data, int load_idx); 446 447 /** Executes the store at the given index. */ 448 template <class T> 449 Fault write(Request *req, T &data, int store_idx); 450 451 /** Returns the index of the head load instruction. */ 452 int getLoadHead() { return loadHead; } 453 /** Returns the sequence number of the head load instruction. */ 454 InstSeqNum getLoadHeadSeqNum() 455 { 456 if (loadQueue[loadHead]) { 457 return loadQueue[loadHead]->seqNum; 458 } else { 459 return 0; 460 } 461 462 } 463 464 /** Returns the index of the head store instruction. */ 465 int getStoreHead() { return storeHead; } 466 /** Returns the sequence number of the head store instruction. */ 467 InstSeqNum getStoreHeadSeqNum() 468 { 469 if (storeQueue[storeHead].inst) { 470 return storeQueue[storeHead].inst->seqNum; 471 } else { 472 return 0; 473 } 474 475 } 476 477 /** Returns whether or not the LSQ unit is stalled. */ 478 bool isStalled() { return stalled; } 479}; 480 481template <class Impl> 482template <class T> 483Fault 484LSQUnit<Impl>::read(Request *req, T &data, int load_idx) 485{ 486 DynInstPtr load_inst = loadQueue[load_idx]; 487 488 assert(load_inst); 489 490 assert(!load_inst->isExecuted()); 491 492 // Make sure this isn't an uncacheable access 493 // A bit of a hackish way to get uncached accesses to work only if they're 494 // at the head of the LSQ and are ready to commit (at the head of the ROB 495 // too). 496 if (req->isUncacheable() && 497 (load_idx != loadHead || !load_inst->isAtCommit())) { 498 iewStage->rescheduleMemInst(load_inst); 499 ++lsqRescheduledLoads; 500 return TheISA::genMachineCheckFault(); 501 } 502 503 // Check the SQ for any previous stores that might lead to forwarding 504 int store_idx = load_inst->sqIdx; 505 506 int store_size = 0; 507 508 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, " 509 "storeHead: %i addr: %#x\n", 510 load_idx, store_idx, storeHead, req->getPaddr()); 511 512#if FULL_SYSTEM 513 if (req->isLocked()) {
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513 cpu->lockAddr = req->getPaddr(); 514 cpu->lockFlag = true;
| 514 // Disable recording the result temporarily. Writing to misc 515 // regs normally updates the result, but this is not the 516 // desired behavior when handling store conditionals. 517 load_inst->recordResult = false; 518 TheISA::handleLockedRead(load_inst.get(), req); 519 load_inst->recordResult = true;
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515 } 516#endif 517 518 while (store_idx != -1) { 519 // End once we've reached the top of the LSQ 520 if (store_idx == storeWBIdx) { 521 break; 522 } 523 524 // Move the index to one younger 525 if (--store_idx < 0) 526 store_idx += SQEntries; 527 528 assert(storeQueue[store_idx].inst); 529 530 store_size = storeQueue[store_idx].size; 531 532 if (store_size == 0) 533 continue; 534 535 // Check if the store data is within the lower and upper bounds of 536 // addresses that the request needs. 537 bool store_has_lower_limit = 538 req->getVaddr() >= storeQueue[store_idx].inst->effAddr; 539 bool store_has_upper_limit = 540 (req->getVaddr() + req->getSize()) <= 541 (storeQueue[store_idx].inst->effAddr + store_size); 542 bool lower_load_has_store_part = 543 req->getVaddr() < (storeQueue[store_idx].inst->effAddr + 544 store_size); 545 bool upper_load_has_store_part = 546 (req->getVaddr() + req->getSize()) > 547 storeQueue[store_idx].inst->effAddr; 548 549 // If the store's data has all of the data needed, we can forward. 550 if (store_has_lower_limit && store_has_upper_limit) { 551 // Get shift amount for offset into the store's data. 552 int shift_amt = req->getVaddr() & (store_size - 1); 553 // @todo: Magic number, assumes byte addressing 554 shift_amt = shift_amt << 3; 555 556 // Cast this to type T? 557 data = storeQueue[store_idx].data >> shift_amt; 558 559 assert(!load_inst->memData); 560 load_inst->memData = new uint8_t[64]; 561 562 memcpy(load_inst->memData, &data, req->getSize()); 563 564 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to " 565 "addr %#x, data %#x\n", 566 store_idx, req->getVaddr(), data); 567 568 PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast); 569 data_pkt->dataStatic(load_inst->memData); 570 571 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this); 572 573 // We'll say this has a 1 cycle load-store forwarding latency 574 // for now. 575 // @todo: Need to make this a parameter. 576 wb->schedule(curTick); 577 578 ++lsqForwLoads; 579 return NoFault; 580 } else if ((store_has_lower_limit && lower_load_has_store_part) || 581 (store_has_upper_limit && upper_load_has_store_part) || 582 (lower_load_has_store_part && upper_load_has_store_part)) { 583 // This is the partial store-load forwarding case where a store 584 // has only part of the load's data. 585 586 // If it's already been written back, then don't worry about 587 // stalling on it. 588 if (storeQueue[store_idx].completed) { 589 continue; 590 } 591 592 // Must stall load and force it to retry, so long as it's the oldest 593 // load that needs to do so. 594 if (!stalled || 595 (stalled && 596 load_inst->seqNum < 597 loadQueue[stallingLoadIdx]->seqNum)) { 598 stalled = true; 599 stallingStoreIsn = storeQueue[store_idx].inst->seqNum; 600 stallingLoadIdx = load_idx; 601 } 602 603 // Tell IQ/mem dep unit that this instruction will need to be 604 // rescheduled eventually 605 iewStage->rescheduleMemInst(load_inst); 606 iewStage->decrWb(load_inst->seqNum); 607 ++lsqRescheduledLoads; 608 609 // Do not generate a writeback event as this instruction is not 610 // complete. 611 DPRINTF(LSQUnit, "Load-store forwarding mis-match. " 612 "Store idx %i to load addr %#x\n", 613 store_idx, req->getVaddr()); 614 615 ++lsqBlockedLoads; 616 return NoFault; 617 } 618 } 619 620 // If there's no forwarding case, then go access memory 621 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %#x\n", 622 load_inst->seqNum, load_inst->readPC()); 623 624 assert(!load_inst->memData); 625 load_inst->memData = new uint8_t[64]; 626 627 ++usedPorts; 628 629 // if we the cache is not blocked, do cache access 630 if (!lsq->cacheBlocked()) { 631 PacketPtr data_pkt = 632 new Packet(req, Packet::ReadReq, Packet::Broadcast); 633 data_pkt->dataStatic(load_inst->memData); 634 635 LSQSenderState *state = new LSQSenderState; 636 state->isLoad = true; 637 state->idx = load_idx; 638 state->inst = load_inst; 639 data_pkt->senderState = state; 640 641 if (!dcachePort->sendTiming(data_pkt)) { 642 Packet::Result result = data_pkt->result; 643 644 // Delete state and data packet because a load retry 645 // initiates a pipeline restart; it does not retry. 646 delete state; 647 delete data_pkt; 648 649 if (result == Packet::BadAddress) { 650 return TheISA::genMachineCheckFault(); 651 } 652 653 // If the access didn't succeed, tell the LSQ by setting 654 // the retry thread id. 655 lsq->setRetryTid(lsqID); 656 } 657 } 658 659 // If the cache was blocked, or has become blocked due to the access, 660 // handle it. 661 if (lsq->cacheBlocked()) { 662 ++lsqCacheBlocked; 663 664 iewStage->decrWb(load_inst->seqNum); 665 // There's an older load that's already going to squash. 666 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum) 667 return NoFault; 668 669 // Record that the load was blocked due to memory. This 670 // load will squash all instructions after it, be 671 // refetched, and re-executed. 672 isLoadBlocked = true; 673 loadBlockedHandled = false; 674 blockedLoadSeqNum = load_inst->seqNum; 675 // No fault occurred, even though the interface is blocked. 676 return NoFault; 677 } 678 679 return NoFault; 680} 681 682template <class Impl> 683template <class T> 684Fault 685LSQUnit<Impl>::write(Request *req, T &data, int store_idx) 686{ 687 assert(storeQueue[store_idx].inst); 688 689 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x" 690 " | storeHead:%i [sn:%i]\n", 691 store_idx, req->getPaddr(), data, storeHead, 692 storeQueue[store_idx].inst->seqNum); 693 694 storeQueue[store_idx].req = req; 695 storeQueue[store_idx].size = sizeof(T); 696 storeQueue[store_idx].data = data; 697 698 // This function only writes the data to the store queue, so no fault 699 // can happen here. 700 return NoFault; 701} 702 703#endif // __CPU_O3_LSQ_UNIT_HH__
| 520 } 521#endif 522 523 while (store_idx != -1) { 524 // End once we've reached the top of the LSQ 525 if (store_idx == storeWBIdx) { 526 break; 527 } 528 529 // Move the index to one younger 530 if (--store_idx < 0) 531 store_idx += SQEntries; 532 533 assert(storeQueue[store_idx].inst); 534 535 store_size = storeQueue[store_idx].size; 536 537 if (store_size == 0) 538 continue; 539 540 // Check if the store data is within the lower and upper bounds of 541 // addresses that the request needs. 542 bool store_has_lower_limit = 543 req->getVaddr() >= storeQueue[store_idx].inst->effAddr; 544 bool store_has_upper_limit = 545 (req->getVaddr() + req->getSize()) <= 546 (storeQueue[store_idx].inst->effAddr + store_size); 547 bool lower_load_has_store_part = 548 req->getVaddr() < (storeQueue[store_idx].inst->effAddr + 549 store_size); 550 bool upper_load_has_store_part = 551 (req->getVaddr() + req->getSize()) > 552 storeQueue[store_idx].inst->effAddr; 553 554 // If the store's data has all of the data needed, we can forward. 555 if (store_has_lower_limit && store_has_upper_limit) { 556 // Get shift amount for offset into the store's data. 557 int shift_amt = req->getVaddr() & (store_size - 1); 558 // @todo: Magic number, assumes byte addressing 559 shift_amt = shift_amt << 3; 560 561 // Cast this to type T? 562 data = storeQueue[store_idx].data >> shift_amt; 563 564 assert(!load_inst->memData); 565 load_inst->memData = new uint8_t[64]; 566 567 memcpy(load_inst->memData, &data, req->getSize()); 568 569 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to " 570 "addr %#x, data %#x\n", 571 store_idx, req->getVaddr(), data); 572 573 PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast); 574 data_pkt->dataStatic(load_inst->memData); 575 576 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this); 577 578 // We'll say this has a 1 cycle load-store forwarding latency 579 // for now. 580 // @todo: Need to make this a parameter. 581 wb->schedule(curTick); 582 583 ++lsqForwLoads; 584 return NoFault; 585 } else if ((store_has_lower_limit && lower_load_has_store_part) || 586 (store_has_upper_limit && upper_load_has_store_part) || 587 (lower_load_has_store_part && upper_load_has_store_part)) { 588 // This is the partial store-load forwarding case where a store 589 // has only part of the load's data. 590 591 // If it's already been written back, then don't worry about 592 // stalling on it. 593 if (storeQueue[store_idx].completed) { 594 continue; 595 } 596 597 // Must stall load and force it to retry, so long as it's the oldest 598 // load that needs to do so. 599 if (!stalled || 600 (stalled && 601 load_inst->seqNum < 602 loadQueue[stallingLoadIdx]->seqNum)) { 603 stalled = true; 604 stallingStoreIsn = storeQueue[store_idx].inst->seqNum; 605 stallingLoadIdx = load_idx; 606 } 607 608 // Tell IQ/mem dep unit that this instruction will need to be 609 // rescheduled eventually 610 iewStage->rescheduleMemInst(load_inst); 611 iewStage->decrWb(load_inst->seqNum); 612 ++lsqRescheduledLoads; 613 614 // Do not generate a writeback event as this instruction is not 615 // complete. 616 DPRINTF(LSQUnit, "Load-store forwarding mis-match. " 617 "Store idx %i to load addr %#x\n", 618 store_idx, req->getVaddr()); 619 620 ++lsqBlockedLoads; 621 return NoFault; 622 } 623 } 624 625 // If there's no forwarding case, then go access memory 626 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %#x\n", 627 load_inst->seqNum, load_inst->readPC()); 628 629 assert(!load_inst->memData); 630 load_inst->memData = new uint8_t[64]; 631 632 ++usedPorts; 633 634 // if we the cache is not blocked, do cache access 635 if (!lsq->cacheBlocked()) { 636 PacketPtr data_pkt = 637 new Packet(req, Packet::ReadReq, Packet::Broadcast); 638 data_pkt->dataStatic(load_inst->memData); 639 640 LSQSenderState *state = new LSQSenderState; 641 state->isLoad = true; 642 state->idx = load_idx; 643 state->inst = load_inst; 644 data_pkt->senderState = state; 645 646 if (!dcachePort->sendTiming(data_pkt)) { 647 Packet::Result result = data_pkt->result; 648 649 // Delete state and data packet because a load retry 650 // initiates a pipeline restart; it does not retry. 651 delete state; 652 delete data_pkt; 653 654 if (result == Packet::BadAddress) { 655 return TheISA::genMachineCheckFault(); 656 } 657 658 // If the access didn't succeed, tell the LSQ by setting 659 // the retry thread id. 660 lsq->setRetryTid(lsqID); 661 } 662 } 663 664 // If the cache was blocked, or has become blocked due to the access, 665 // handle it. 666 if (lsq->cacheBlocked()) { 667 ++lsqCacheBlocked; 668 669 iewStage->decrWb(load_inst->seqNum); 670 // There's an older load that's already going to squash. 671 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum) 672 return NoFault; 673 674 // Record that the load was blocked due to memory. This 675 // load will squash all instructions after it, be 676 // refetched, and re-executed. 677 isLoadBlocked = true; 678 loadBlockedHandled = false; 679 blockedLoadSeqNum = load_inst->seqNum; 680 // No fault occurred, even though the interface is blocked. 681 return NoFault; 682 } 683 684 return NoFault; 685} 686 687template <class Impl> 688template <class T> 689Fault 690LSQUnit<Impl>::write(Request *req, T &data, int store_idx) 691{ 692 assert(storeQueue[store_idx].inst); 693 694 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x" 695 " | storeHead:%i [sn:%i]\n", 696 store_idx, req->getPaddr(), data, storeHead, 697 storeQueue[store_idx].inst->seqNum); 698 699 storeQueue[store_idx].req = req; 700 storeQueue[store_idx].size = sizeof(T); 701 storeQueue[store_idx].data = data; 702 703 // This function only writes the data to the store queue, so no fault 704 // can happen here. 705 return NoFault; 706} 707 708#endif // __CPU_O3_LSQ_UNIT_HH__
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