1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_LSQ_UNIT_HH__ 33#define __CPU_O3_LSQ_UNIT_HH__ 34 35#include <algorithm> 36#include <map> 37#include <queue> 38 39#include "arch/faults.hh" 40#include "config/full_system.hh" 41#include "base/hashmap.hh" 42#include "cpu/inst_seq.hh" 43#include "mem/packet.hh" 44#include "mem/port.hh"
| 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_LSQ_UNIT_HH__ 33#define __CPU_O3_LSQ_UNIT_HH__ 34 35#include <algorithm> 36#include <map> 37#include <queue> 38 39#include "arch/faults.hh" 40#include "config/full_system.hh" 41#include "base/hashmap.hh" 42#include "cpu/inst_seq.hh" 43#include "mem/packet.hh" 44#include "mem/port.hh"
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45//#include "mem/page_table.hh" 46//#include "sim/debug.hh" 47//#include "sim/sim_object.hh"
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48 49/** 50 * Class that implements the actual LQ and SQ for each specific 51 * thread. Both are circular queues; load entries are freed upon 52 * committing, while store entries are freed once they writeback. The 53 * LSQUnit tracks if there are memory ordering violations, and also 54 * detects partial load to store forwarding cases (a store only has 55 * part of a load's data) that requires the load to wait until the 56 * store writes back. In the former case it holds onto the instruction 57 * until the dependence unit looks at it, and in the latter it stalls 58 * the LSQ until the store writes back. At that point the load is 59 * replayed. 60 */ 61template <class Impl> 62class LSQUnit { 63 protected: 64 typedef TheISA::IntReg IntReg; 65 public: 66 typedef typename Impl::Params Params; 67 typedef typename Impl::FullCPU FullCPU; 68 typedef typename Impl::DynInstPtr DynInstPtr; 69 typedef typename Impl::CPUPol::IEW IEW; 70 typedef typename Impl::CPUPol::IssueStruct IssueStruct; 71 72 public: 73 /** Constructs an LSQ unit. init() must be called prior to use. */ 74 LSQUnit(); 75 76 /** Initializes the LSQ unit with the specified number of entries. */ 77 void init(Params *params, unsigned maxLQEntries, 78 unsigned maxSQEntries, unsigned id); 79 80 /** Returns the name of the LSQ unit. */ 81 std::string name() const; 82 83 /** Sets the CPU pointer. */ 84 void setCPU(FullCPU *cpu_ptr); 85 86 /** Sets the IEW stage pointer. */ 87 void setIEW(IEW *iew_ptr) 88 { iewStage = iew_ptr; } 89
| 45 46/** 47 * Class that implements the actual LQ and SQ for each specific 48 * thread. Both are circular queues; load entries are freed upon 49 * committing, while store entries are freed once they writeback. The 50 * LSQUnit tracks if there are memory ordering violations, and also 51 * detects partial load to store forwarding cases (a store only has 52 * part of a load's data) that requires the load to wait until the 53 * store writes back. In the former case it holds onto the instruction 54 * until the dependence unit looks at it, and in the latter it stalls 55 * the LSQ until the store writes back. At that point the load is 56 * replayed. 57 */ 58template <class Impl> 59class LSQUnit { 60 protected: 61 typedef TheISA::IntReg IntReg; 62 public: 63 typedef typename Impl::Params Params; 64 typedef typename Impl::FullCPU FullCPU; 65 typedef typename Impl::DynInstPtr DynInstPtr; 66 typedef typename Impl::CPUPol::IEW IEW; 67 typedef typename Impl::CPUPol::IssueStruct IssueStruct; 68 69 public: 70 /** Constructs an LSQ unit. init() must be called prior to use. */ 71 LSQUnit(); 72 73 /** Initializes the LSQ unit with the specified number of entries. */ 74 void init(Params *params, unsigned maxLQEntries, 75 unsigned maxSQEntries, unsigned id); 76 77 /** Returns the name of the LSQ unit. */ 78 std::string name() const; 79 80 /** Sets the CPU pointer. */ 81 void setCPU(FullCPU *cpu_ptr); 82 83 /** Sets the IEW stage pointer. */ 84 void setIEW(IEW *iew_ptr) 85 { iewStage = iew_ptr; } 86
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90 /** Sets the page table pointer. */ 91// void setPageTable(PageTable *pt_ptr); 92
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93 /** Switches out LSQ unit. */ 94 void switchOut(); 95 96 /** Takes over from another CPU's thread. */ 97 void takeOverFrom(); 98 99 /** Returns if the LSQ is switched out. */ 100 bool isSwitchedOut() { return switchedOut; } 101 102 /** Ticks the LSQ unit, which in this case only resets the number of 103 * used cache ports. 104 * @todo: Move the number of used ports up to the LSQ level so it can 105 * be shared by all LSQ units. 106 */ 107 void tick() { usedPorts = 0; } 108 109 /** Inserts an instruction. */ 110 void insert(DynInstPtr &inst); 111 /** Inserts a load instruction. */ 112 void insertLoad(DynInstPtr &load_inst); 113 /** Inserts a store instruction. */ 114 void insertStore(DynInstPtr &store_inst); 115 116 /** Executes a load instruction. */ 117 Fault executeLoad(DynInstPtr &inst); 118 119 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; } 120 /** Executes a store instruction. */ 121 Fault executeStore(DynInstPtr &inst); 122 123 /** Commits the head load. */ 124 void commitLoad(); 125 /** Commits loads older than a specific sequence number. */ 126 void commitLoads(InstSeqNum &youngest_inst); 127 128 /** Commits stores older than a specific sequence number. */ 129 void commitStores(InstSeqNum &youngest_inst); 130 131 /** Writes back stores. */ 132 void writebackStores(); 133 134 void completeDataAccess(PacketPtr pkt); 135 136 // @todo: Include stats in the LSQ unit. 137 //void regStats(); 138 139 /** Clears all the entries in the LQ. */ 140 void clearLQ(); 141 142 /** Clears all the entries in the SQ. */ 143 void clearSQ(); 144 145 /** Resizes the LQ to a given size. */ 146 void resizeLQ(unsigned size); 147 148 /** Resizes the SQ to a given size. */ 149 void resizeSQ(unsigned size); 150 151 /** Squashes all instructions younger than a specific sequence number. */ 152 void squash(const InstSeqNum &squashed_num); 153 154 /** Returns if there is a memory ordering violation. Value is reset upon 155 * call to getMemDepViolator(). 156 */ 157 bool violation() { return memDepViolator; } 158 159 /** Returns the memory ordering violator. */ 160 DynInstPtr getMemDepViolator(); 161 162 /** Returns if a load became blocked due to the memory system. */ 163 bool loadBlocked() 164 { return isLoadBlocked; } 165 166 /** Clears the signal that a load became blocked. */ 167 void clearLoadBlocked() 168 { isLoadBlocked = false; } 169 170 /** Returns if the blocked load was handled. */ 171 bool isLoadBlockedHandled() 172 { return loadBlockedHandled; } 173 174 /** Records the blocked load as being handled. */ 175 void setLoadBlockedHandled() 176 { loadBlockedHandled = true; } 177 178 /** Returns the number of free entries (min of free LQ and SQ entries). */ 179 unsigned numFreeEntries(); 180 181 /** Returns the number of loads ready to execute. */ 182 int numLoadsReady(); 183 184 /** Returns the number of loads in the LQ. */ 185 int numLoads() { return loads; } 186 187 /** Returns the number of stores in the SQ. */ 188 int numStores() { return stores; } 189 190 /** Returns if either the LQ or SQ is full. */ 191 bool isFull() { return lqFull() || sqFull(); } 192 193 /** Returns if the LQ is full. */ 194 bool lqFull() { return loads >= (LQEntries - 1); } 195 196 /** Returns if the SQ is full. */ 197 bool sqFull() { return stores >= (SQEntries - 1); } 198 199 /** Returns the number of instructions in the LSQ. */ 200 unsigned getCount() { return loads + stores; } 201 202 /** Returns if there are any stores to writeback. */ 203 bool hasStoresToWB() { return storesToWB; } 204 205 /** Returns the number of stores to writeback. */ 206 int numStoresToWB() { return storesToWB; } 207 208 /** Returns if the LSQ unit will writeback on this cycle. */ 209 bool willWB() { return storeQueue[storeWBIdx].canWB && 210 !storeQueue[storeWBIdx].completed && 211 !isStoreBlocked; } 212 213 private:
| 87 /** Switches out LSQ unit. */ 88 void switchOut(); 89 90 /** Takes over from another CPU's thread. */ 91 void takeOverFrom(); 92 93 /** Returns if the LSQ is switched out. */ 94 bool isSwitchedOut() { return switchedOut; } 95 96 /** Ticks the LSQ unit, which in this case only resets the number of 97 * used cache ports. 98 * @todo: Move the number of used ports up to the LSQ level so it can 99 * be shared by all LSQ units. 100 */ 101 void tick() { usedPorts = 0; } 102 103 /** Inserts an instruction. */ 104 void insert(DynInstPtr &inst); 105 /** Inserts a load instruction. */ 106 void insertLoad(DynInstPtr &load_inst); 107 /** Inserts a store instruction. */ 108 void insertStore(DynInstPtr &store_inst); 109 110 /** Executes a load instruction. */ 111 Fault executeLoad(DynInstPtr &inst); 112 113 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; } 114 /** Executes a store instruction. */ 115 Fault executeStore(DynInstPtr &inst); 116 117 /** Commits the head load. */ 118 void commitLoad(); 119 /** Commits loads older than a specific sequence number. */ 120 void commitLoads(InstSeqNum &youngest_inst); 121 122 /** Commits stores older than a specific sequence number. */ 123 void commitStores(InstSeqNum &youngest_inst); 124 125 /** Writes back stores. */ 126 void writebackStores(); 127 128 void completeDataAccess(PacketPtr pkt); 129 130 // @todo: Include stats in the LSQ unit. 131 //void regStats(); 132 133 /** Clears all the entries in the LQ. */ 134 void clearLQ(); 135 136 /** Clears all the entries in the SQ. */ 137 void clearSQ(); 138 139 /** Resizes the LQ to a given size. */ 140 void resizeLQ(unsigned size); 141 142 /** Resizes the SQ to a given size. */ 143 void resizeSQ(unsigned size); 144 145 /** Squashes all instructions younger than a specific sequence number. */ 146 void squash(const InstSeqNum &squashed_num); 147 148 /** Returns if there is a memory ordering violation. Value is reset upon 149 * call to getMemDepViolator(). 150 */ 151 bool violation() { return memDepViolator; } 152 153 /** Returns the memory ordering violator. */ 154 DynInstPtr getMemDepViolator(); 155 156 /** Returns if a load became blocked due to the memory system. */ 157 bool loadBlocked() 158 { return isLoadBlocked; } 159 160 /** Clears the signal that a load became blocked. */ 161 void clearLoadBlocked() 162 { isLoadBlocked = false; } 163 164 /** Returns if the blocked load was handled. */ 165 bool isLoadBlockedHandled() 166 { return loadBlockedHandled; } 167 168 /** Records the blocked load as being handled. */ 169 void setLoadBlockedHandled() 170 { loadBlockedHandled = true; } 171 172 /** Returns the number of free entries (min of free LQ and SQ entries). */ 173 unsigned numFreeEntries(); 174 175 /** Returns the number of loads ready to execute. */ 176 int numLoadsReady(); 177 178 /** Returns the number of loads in the LQ. */ 179 int numLoads() { return loads; } 180 181 /** Returns the number of stores in the SQ. */ 182 int numStores() { return stores; } 183 184 /** Returns if either the LQ or SQ is full. */ 185 bool isFull() { return lqFull() || sqFull(); } 186 187 /** Returns if the LQ is full. */ 188 bool lqFull() { return loads >= (LQEntries - 1); } 189 190 /** Returns if the SQ is full. */ 191 bool sqFull() { return stores >= (SQEntries - 1); } 192 193 /** Returns the number of instructions in the LSQ. */ 194 unsigned getCount() { return loads + stores; } 195 196 /** Returns if there are any stores to writeback. */ 197 bool hasStoresToWB() { return storesToWB; } 198 199 /** Returns the number of stores to writeback. */ 200 int numStoresToWB() { return storesToWB; } 201 202 /** Returns if the LSQ unit will writeback on this cycle. */ 203 bool willWB() { return storeQueue[storeWBIdx].canWB && 204 !storeQueue[storeWBIdx].completed && 205 !isStoreBlocked; } 206 207 private:
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| 208 /** Writes back the instruction, sending it to IEW. */
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214 void writeback(DynInstPtr &inst, PacketPtr pkt); 215
| 209 void writeback(DynInstPtr &inst, PacketPtr pkt); 210
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| 211 /** Handles completing the send of a store to memory. */
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216 void storePostSend(Packet *pkt); 217 218 /** Completes the store at the specified index. */ 219 void completeStore(int store_idx); 220 221 /** Handles doing the retry. */ 222 void recvRetry(); 223 224 /** Increments the given store index (circular queue). */ 225 inline void incrStIdx(int &store_idx); 226 /** Decrements the given store index (circular queue). */ 227 inline void decrStIdx(int &store_idx); 228 /** Increments the given load index (circular queue). */ 229 inline void incrLdIdx(int &load_idx); 230 /** Decrements the given load index (circular queue). */ 231 inline void decrLdIdx(int &load_idx); 232 233 public: 234 /** Debugging function to dump instructions in the LSQ. */ 235 void dumpInsts(); 236 237 private: 238 /** Pointer to the CPU. */ 239 FullCPU *cpu; 240 241 /** Pointer to the IEW stage. */ 242 IEW *iewStage; 243
| 212 void storePostSend(Packet *pkt); 213 214 /** Completes the store at the specified index. */ 215 void completeStore(int store_idx); 216 217 /** Handles doing the retry. */ 218 void recvRetry(); 219 220 /** Increments the given store index (circular queue). */ 221 inline void incrStIdx(int &store_idx); 222 /** Decrements the given store index (circular queue). */ 223 inline void decrStIdx(int &store_idx); 224 /** Increments the given load index (circular queue). */ 225 inline void incrLdIdx(int &load_idx); 226 /** Decrements the given load index (circular queue). */ 227 inline void decrLdIdx(int &load_idx); 228 229 public: 230 /** Debugging function to dump instructions in the LSQ. */ 231 void dumpInsts(); 232 233 private: 234 /** Pointer to the CPU. */ 235 FullCPU *cpu; 236 237 /** Pointer to the IEW stage. */ 238 IEW *iewStage; 239
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| 240 /** Pointer to memory object. */
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244 MemObject *mem; 245
| 241 MemObject *mem; 242
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| 243 /** DcachePort class for this LSQ Unit. Handles doing the 244 * communication with the cache/memory. 245 * @todo: Needs to be moved to the LSQ level and have some sort 246 * of arbitration. 247 */
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246 class DcachePort : public Port 247 { 248 protected:
| 248 class DcachePort : public Port 249 { 250 protected:
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| 251 /** Pointer to CPU. */
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249 FullCPU *cpu;
| 252 FullCPU *cpu;
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| 253 /** Pointer to LSQ. */
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250 LSQUnit *lsq; 251 252 public:
| 254 LSQUnit *lsq; 255 256 public:
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| 257 /** Default constructor. */
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253 DcachePort(FullCPU *_cpu, LSQUnit *_lsq) 254 : Port(_lsq->name() + "-dport"), cpu(_cpu), lsq(_lsq) 255 { } 256 257 protected:
| 258 DcachePort(FullCPU *_cpu, LSQUnit *_lsq) 259 : Port(_lsq->name() + "-dport"), cpu(_cpu), lsq(_lsq) 260 { } 261 262 protected:
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| 263 /** Atomic version of receive. Panics. */
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258 virtual Tick recvAtomic(PacketPtr pkt); 259
| 264 virtual Tick recvAtomic(PacketPtr pkt); 265
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| 266 /** Functional version of receive. Panics. */
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260 virtual void recvFunctional(PacketPtr pkt); 261
| 267 virtual void recvFunctional(PacketPtr pkt); 268
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| 269 /** Receives status change. Other than range changing, panics. */
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262 virtual void recvStatusChange(Status status); 263
| 270 virtual void recvStatusChange(Status status); 271
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| 272 /** Returns the address ranges of this device. */
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264 virtual void getDeviceAddressRanges(AddrRangeList &resp, 265 AddrRangeList &snoop) 266 { resp.clear(); snoop.clear(); } 267
| 273 virtual void getDeviceAddressRanges(AddrRangeList &resp, 274 AddrRangeList &snoop) 275 { resp.clear(); snoop.clear(); } 276
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| 277 /** Timing version of receive. Handles writing back and 278 * completing the load or store that has returned from 279 * memory. */
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268 virtual bool recvTiming(PacketPtr pkt); 269
| 280 virtual bool recvTiming(PacketPtr pkt); 281
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| 282 /** Handles doing a retry of the previous send. */
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270 virtual void recvRetry(); 271 }; 272 273 /** Pointer to the D-cache. */ 274 DcachePort *dcachePort; 275
| 283 virtual void recvRetry(); 284 }; 285 286 /** Pointer to the D-cache. */ 287 DcachePort *dcachePort; 288
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| 289 /** Derived class to hold any sender state the LSQ needs. */
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276 class LSQSenderState : public Packet::SenderState 277 { 278 public:
| 290 class LSQSenderState : public Packet::SenderState 291 { 292 public:
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| 293 /** Default constructor. */
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279 LSQSenderState() 280 : noWB(false) 281 { } 282
| 294 LSQSenderState() 295 : noWB(false) 296 { } 297
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283// protected:
| 298 /** Instruction who initiated the access to memory. */
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284 DynInstPtr inst;
| 299 DynInstPtr inst;
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| 300 /** Whether or not it is a load. */
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285 bool isLoad;
| 301 bool isLoad;
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| 302 /** The LQ/SQ index of the instruction. */
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286 int idx;
| 303 int idx;
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| 304 /** Whether or not the instruction will need to writeback. */
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287 bool noWB; 288 }; 289
| 305 bool noWB; 306 }; 307
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290 /** Pointer to the page table. */ 291// PageTable *pTable; 292
| 308 /** Writeback event, specifically for when stores forward data to loads. */
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293 class WritebackEvent : public Event { 294 public: 295 /** Constructs a writeback event. */ 296 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr); 297 298 /** Processes the writeback event. */ 299 void process(); 300 301 /** Returns the description of this event. */ 302 const char *description(); 303 304 private:
| 309 class WritebackEvent : public Event { 310 public: 311 /** Constructs a writeback event. */ 312 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr); 313 314 /** Processes the writeback event. */ 315 void process(); 316 317 /** Returns the description of this event. */ 318 const char *description(); 319 320 private:
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| 321 /** Instruction whose results are being written back. */
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305 DynInstPtr inst; 306
| 322 DynInstPtr inst; 323
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| 324 /** The packet that would have been sent to memory. */
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307 PacketPtr pkt; 308 309 /** The pointer to the LSQ unit that issued the store. */ 310 LSQUnit<Impl> *lsqPtr; 311 }; 312 313 public: 314 struct SQEntry { 315 /** Constructs an empty store queue entry. */ 316 SQEntry() 317 : inst(NULL), req(NULL), size(0), data(0), 318 canWB(0), committed(0), completed(0) 319 { } 320 321 /** Constructs a store queue entry for a given instruction. */ 322 SQEntry(DynInstPtr &_inst) 323 : inst(_inst), req(NULL), size(0), data(0), 324 canWB(0), committed(0), completed(0) 325 { } 326 327 /** The store instruction. */ 328 DynInstPtr inst; 329 /** The request for the store. */ 330 RequestPtr req; 331 /** The size of the store. */ 332 int size; 333 /** The store data. */ 334 IntReg data; 335 /** Whether or not the store can writeback. */ 336 bool canWB; 337 /** Whether or not the store is committed. */ 338 bool committed; 339 /** Whether or not the store is completed. */ 340 bool completed; 341 }; 342 343 private: 344 /** The LSQUnit thread id. */ 345 unsigned lsqID; 346 347 /** The store queue. */ 348 std::vector<SQEntry> storeQueue; 349 350 /** The load queue. */ 351 std::vector<DynInstPtr> loadQueue; 352 353 /** The number of LQ entries, plus a sentinel entry (circular queue). 354 * @todo: Consider having var that records the true number of LQ entries. 355 */ 356 unsigned LQEntries; 357 /** The number of SQ entries, plus a sentinel entry (circular queue). 358 * @todo: Consider having var that records the true number of SQ entries. 359 */ 360 unsigned SQEntries; 361 362 /** The number of load instructions in the LQ. */ 363 int loads; 364 /** The number of store instructions in the SQ. */ 365 int stores; 366 /** The number of store instructions in the SQ waiting to writeback. */ 367 int storesToWB; 368 369 /** The index of the head instruction in the LQ. */ 370 int loadHead; 371 /** The index of the tail instruction in the LQ. */ 372 int loadTail; 373 374 /** The index of the head instruction in the SQ. */ 375 int storeHead; 376 /** The index of the first instruction that may be ready to be 377 * written back, and has not yet been written back. 378 */ 379 int storeWBIdx; 380 /** The index of the tail instruction in the SQ. */ 381 int storeTail; 382 383 /// @todo Consider moving to a more advanced model with write vs read ports 384 /** The number of cache ports available each cycle. */ 385 int cachePorts; 386 387 /** The number of used cache ports in this cycle. */ 388 int usedPorts; 389 390 /** Is the LSQ switched out. */ 391 bool switchedOut; 392 393 //list<InstSeqNum> mshrSeqNums; 394 395 /** Wire to read information from the issue stage time queue. */ 396 typename TimeBuffer<IssueStruct>::wire fromIssue; 397 398 /** Whether or not the LSQ is stalled. */ 399 bool stalled; 400 /** The store that causes the stall due to partial store to load 401 * forwarding. 402 */ 403 InstSeqNum stallingStoreIsn; 404 /** The index of the above store. */ 405 int stallingLoadIdx; 406
| 325 PacketPtr pkt; 326 327 /** The pointer to the LSQ unit that issued the store. */ 328 LSQUnit<Impl> *lsqPtr; 329 }; 330 331 public: 332 struct SQEntry { 333 /** Constructs an empty store queue entry. */ 334 SQEntry() 335 : inst(NULL), req(NULL), size(0), data(0), 336 canWB(0), committed(0), completed(0) 337 { } 338 339 /** Constructs a store queue entry for a given instruction. */ 340 SQEntry(DynInstPtr &_inst) 341 : inst(_inst), req(NULL), size(0), data(0), 342 canWB(0), committed(0), completed(0) 343 { } 344 345 /** The store instruction. */ 346 DynInstPtr inst; 347 /** The request for the store. */ 348 RequestPtr req; 349 /** The size of the store. */ 350 int size; 351 /** The store data. */ 352 IntReg data; 353 /** Whether or not the store can writeback. */ 354 bool canWB; 355 /** Whether or not the store is committed. */ 356 bool committed; 357 /** Whether or not the store is completed. */ 358 bool completed; 359 }; 360 361 private: 362 /** The LSQUnit thread id. */ 363 unsigned lsqID; 364 365 /** The store queue. */ 366 std::vector<SQEntry> storeQueue; 367 368 /** The load queue. */ 369 std::vector<DynInstPtr> loadQueue; 370 371 /** The number of LQ entries, plus a sentinel entry (circular queue). 372 * @todo: Consider having var that records the true number of LQ entries. 373 */ 374 unsigned LQEntries; 375 /** The number of SQ entries, plus a sentinel entry (circular queue). 376 * @todo: Consider having var that records the true number of SQ entries. 377 */ 378 unsigned SQEntries; 379 380 /** The number of load instructions in the LQ. */ 381 int loads; 382 /** The number of store instructions in the SQ. */ 383 int stores; 384 /** The number of store instructions in the SQ waiting to writeback. */ 385 int storesToWB; 386 387 /** The index of the head instruction in the LQ. */ 388 int loadHead; 389 /** The index of the tail instruction in the LQ. */ 390 int loadTail; 391 392 /** The index of the head instruction in the SQ. */ 393 int storeHead; 394 /** The index of the first instruction that may be ready to be 395 * written back, and has not yet been written back. 396 */ 397 int storeWBIdx; 398 /** The index of the tail instruction in the SQ. */ 399 int storeTail; 400 401 /// @todo Consider moving to a more advanced model with write vs read ports 402 /** The number of cache ports available each cycle. */ 403 int cachePorts; 404 405 /** The number of used cache ports in this cycle. */ 406 int usedPorts; 407 408 /** Is the LSQ switched out. */ 409 bool switchedOut; 410 411 //list<InstSeqNum> mshrSeqNums; 412 413 /** Wire to read information from the issue stage time queue. */ 414 typename TimeBuffer<IssueStruct>::wire fromIssue; 415 416 /** Whether or not the LSQ is stalled. */ 417 bool stalled; 418 /** The store that causes the stall due to partial store to load 419 * forwarding. 420 */ 421 InstSeqNum stallingStoreIsn; 422 /** The index of the above store. */ 423 int stallingLoadIdx; 424
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407 PacketPtr sendingPkt;
| 425 /** The packet that needs to be retried. */ 426 PacketPtr retryPkt;
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408
| 427
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| 428 /** Whehter or not a store is blocked due to the memory system. */
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409 bool isStoreBlocked; 410 411 /** Whether or not a load is blocked due to the memory system. */ 412 bool isLoadBlocked; 413 414 /** Has the blocked load been handled. */ 415 bool loadBlockedHandled; 416 417 /** The sequence number of the blocked load. */ 418 InstSeqNum blockedLoadSeqNum; 419 420 /** The oldest load that caused a memory ordering violation. */ 421 DynInstPtr memDepViolator; 422 423 // Will also need how many read/write ports the Dcache has. Or keep track 424 // of that in stage that is one level up, and only call executeLoad/Store 425 // the appropriate number of times. 426/* 427 // total number of loads forwaded from LSQ stores 428 Stats::Vector<> lsq_forw_loads; 429 430 // total number of loads ignored due to invalid addresses 431 Stats::Vector<> inv_addr_loads; 432 433 // total number of software prefetches ignored due to invalid addresses 434 Stats::Vector<> inv_addr_swpfs; 435 436 // total non-speculative bogus addresses seen (debug var) 437 Counter sim_invalid_addrs; 438 Stats::Vector<> fu_busy; //cumulative fu busy 439 440 // ready loads blocked due to memory disambiguation 441 Stats::Vector<> lsq_blocked_loads; 442 443 Stats::Scalar<> lsqInversion; 444*/ 445 public: 446 /** Executes the load at the given index. */ 447 template <class T> 448 Fault read(Request *req, T &data, int load_idx); 449 450 /** Executes the store at the given index. */ 451 template <class T> 452 Fault write(Request *req, T &data, int store_idx); 453 454 /** Returns the index of the head load instruction. */ 455 int getLoadHead() { return loadHead; } 456 /** Returns the sequence number of the head load instruction. */ 457 InstSeqNum getLoadHeadSeqNum() 458 { 459 if (loadQueue[loadHead]) { 460 return loadQueue[loadHead]->seqNum; 461 } else { 462 return 0; 463 } 464 465 } 466 467 /** Returns the index of the head store instruction. */ 468 int getStoreHead() { return storeHead; } 469 /** Returns the sequence number of the head store instruction. */ 470 InstSeqNum getStoreHeadSeqNum() 471 { 472 if (storeQueue[storeHead].inst) { 473 return storeQueue[storeHead].inst->seqNum; 474 } else { 475 return 0; 476 } 477 478 } 479 480 /** Returns whether or not the LSQ unit is stalled. */ 481 bool isStalled() { return stalled; } 482}; 483 484template <class Impl> 485template <class T> 486Fault 487LSQUnit<Impl>::read(Request *req, T &data, int load_idx) 488{ 489 DynInstPtr load_inst = loadQueue[load_idx]; 490 491 assert(load_inst); 492 493 assert(!load_inst->isExecuted()); 494 495 // Make sure this isn't an uncacheable access 496 // A bit of a hackish way to get uncached accesses to work only if they're 497 // at the head of the LSQ and are ready to commit (at the head of the ROB 498 // too). 499 if (req->getFlags() & UNCACHEABLE && 500 (load_idx != loadHead || !load_inst->reachedCommit)) { 501 iewStage->rescheduleMemInst(load_inst); 502 return TheISA::genMachineCheckFault(); 503 } 504 505 // Check the SQ for any previous stores that might lead to forwarding 506 int store_idx = load_inst->sqIdx; 507 508 int store_size = 0; 509 510 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, " 511 "storeHead: %i addr: %#x\n", 512 load_idx, store_idx, storeHead, req->getPaddr()); 513 514#if FULL_SYSTEM 515 if (req->getFlags() & LOCKED) { 516 cpu->lockAddr = req->getPaddr(); 517 cpu->lockFlag = true; 518 } 519#endif 520 521 while (store_idx != -1) { 522 // End once we've reached the top of the LSQ 523 if (store_idx == storeWBIdx) { 524 break; 525 } 526 527 // Move the index to one younger 528 if (--store_idx < 0) 529 store_idx += SQEntries; 530 531 assert(storeQueue[store_idx].inst); 532 533 store_size = storeQueue[store_idx].size; 534 535 if (store_size == 0) 536 continue; 537 538 // Check if the store data is within the lower and upper bounds of 539 // addresses that the request needs. 540 bool store_has_lower_limit = 541 req->getVaddr() >= storeQueue[store_idx].inst->effAddr; 542 bool store_has_upper_limit = 543 (req->getVaddr() + req->getSize()) <= 544 (storeQueue[store_idx].inst->effAddr + store_size); 545 bool lower_load_has_store_part = 546 req->getVaddr() < (storeQueue[store_idx].inst->effAddr + 547 store_size); 548 bool upper_load_has_store_part = 549 (req->getVaddr() + req->getSize()) > 550 storeQueue[store_idx].inst->effAddr; 551 552 // If the store's data has all of the data needed, we can forward. 553 if (store_has_lower_limit && store_has_upper_limit) { 554 // Get shift amount for offset into the store's data. 555 int shift_amt = req->getVaddr() & (store_size - 1); 556 // @todo: Magic number, assumes byte addressing 557 shift_amt = shift_amt << 3; 558 559 // Cast this to type T? 560 data = storeQueue[store_idx].data >> shift_amt; 561 562 assert(!load_inst->memData); 563 load_inst->memData = new uint8_t[64]; 564 565 memcpy(load_inst->memData, &data, req->getSize()); 566 567 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to " 568 "addr %#x, data %#x\n", 569 store_idx, req->getVaddr(), data); 570 571 PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast); 572 data_pkt->dataStatic(load_inst->memData); 573 574 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this); 575 576 // We'll say this has a 1 cycle load-store forwarding latency 577 // for now. 578 // @todo: Need to make this a parameter. 579 wb->schedule(curTick); 580 581 // Should keep track of stat for forwarded data 582 return NoFault; 583 } else if ((store_has_lower_limit && lower_load_has_store_part) || 584 (store_has_upper_limit && upper_load_has_store_part) || 585 (lower_load_has_store_part && upper_load_has_store_part)) { 586 // This is the partial store-load forwarding case where a store 587 // has only part of the load's data. 588 589 // If it's already been written back, then don't worry about 590 // stalling on it. 591 if (storeQueue[store_idx].completed) { 592 continue; 593 } 594 595 // Must stall load and force it to retry, so long as it's the oldest 596 // load that needs to do so. 597 if (!stalled || 598 (stalled && 599 load_inst->seqNum < 600 loadQueue[stallingLoadIdx]->seqNum)) { 601 stalled = true; 602 stallingStoreIsn = storeQueue[store_idx].inst->seqNum; 603 stallingLoadIdx = load_idx; 604 } 605 606 // Tell IQ/mem dep unit that this instruction will need to be 607 // rescheduled eventually 608 iewStage->rescheduleMemInst(load_inst); 609 610 // Do not generate a writeback event as this instruction is not 611 // complete. 612 DPRINTF(LSQUnit, "Load-store forwarding mis-match. " 613 "Store idx %i to load addr %#x\n", 614 store_idx, req->getVaddr()); 615 616 return NoFault; 617 } 618 } 619 620 // If there's no forwarding case, then go access memory 621 DPRINTF(LSQUnit, "Doing functional access for inst [sn:%lli] PC %#x\n", 622 load_inst->seqNum, load_inst->readPC()); 623 624 assert(!load_inst->memData); 625 load_inst->memData = new uint8_t[64]; 626 627 ++usedPorts; 628 629 DPRINTF(LSQUnit, "Doing timing access for inst PC %#x\n", 630 load_inst->readPC()); 631 632 PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast); 633 data_pkt->dataStatic(load_inst->memData); 634 635 LSQSenderState *state = new LSQSenderState; 636 state->isLoad = true; 637 state->idx = load_idx; 638 state->inst = load_inst; 639 data_pkt->senderState = state; 640 641 // if we have a cache, do cache access too 642 if (!dcachePort->sendTiming(data_pkt)) { 643 // There's an older load that's already going to squash. 644 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum) 645 return NoFault; 646 647 // Record that the load was blocked due to memory. This 648 // load will squash all instructions after it, be 649 // refetched, and re-executed. 650 isLoadBlocked = true; 651 loadBlockedHandled = false; 652 blockedLoadSeqNum = load_inst->seqNum; 653 // No fault occurred, even though the interface is blocked. 654 return NoFault; 655 } 656 657 if (data_pkt->result != Packet::Success) { 658 DPRINTF(LSQUnit, "LSQUnit: D-cache miss!\n"); 659 DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n", 660 load_inst->seqNum); 661 } else { 662 DPRINTF(LSQUnit, "LSQUnit: D-cache hit!\n"); 663 DPRINTF(Activity, "Activity: ld accessing mem hit [sn:%lli]\n", 664 load_inst->seqNum); 665 } 666 667 return NoFault; 668} 669 670template <class Impl> 671template <class T> 672Fault 673LSQUnit<Impl>::write(Request *req, T &data, int store_idx) 674{ 675 assert(storeQueue[store_idx].inst); 676 677 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x" 678 " | storeHead:%i [sn:%i]\n", 679 store_idx, req->getPaddr(), data, storeHead, 680 storeQueue[store_idx].inst->seqNum); 681 682 storeQueue[store_idx].req = req; 683 storeQueue[store_idx].size = sizeof(T); 684 storeQueue[store_idx].data = data; 685 686 // This function only writes the data to the store queue, so no fault 687 // can happen here. 688 return NoFault; 689} 690 691#endif // __CPU_O3_LSQ_UNIT_HH__
| 429 bool isStoreBlocked; 430 431 /** Whether or not a load is blocked due to the memory system. */ 432 bool isLoadBlocked; 433 434 /** Has the blocked load been handled. */ 435 bool loadBlockedHandled; 436 437 /** The sequence number of the blocked load. */ 438 InstSeqNum blockedLoadSeqNum; 439 440 /** The oldest load that caused a memory ordering violation. */ 441 DynInstPtr memDepViolator; 442 443 // Will also need how many read/write ports the Dcache has. Or keep track 444 // of that in stage that is one level up, and only call executeLoad/Store 445 // the appropriate number of times. 446/* 447 // total number of loads forwaded from LSQ stores 448 Stats::Vector<> lsq_forw_loads; 449 450 // total number of loads ignored due to invalid addresses 451 Stats::Vector<> inv_addr_loads; 452 453 // total number of software prefetches ignored due to invalid addresses 454 Stats::Vector<> inv_addr_swpfs; 455 456 // total non-speculative bogus addresses seen (debug var) 457 Counter sim_invalid_addrs; 458 Stats::Vector<> fu_busy; //cumulative fu busy 459 460 // ready loads blocked due to memory disambiguation 461 Stats::Vector<> lsq_blocked_loads; 462 463 Stats::Scalar<> lsqInversion; 464*/ 465 public: 466 /** Executes the load at the given index. */ 467 template <class T> 468 Fault read(Request *req, T &data, int load_idx); 469 470 /** Executes the store at the given index. */ 471 template <class T> 472 Fault write(Request *req, T &data, int store_idx); 473 474 /** Returns the index of the head load instruction. */ 475 int getLoadHead() { return loadHead; } 476 /** Returns the sequence number of the head load instruction. */ 477 InstSeqNum getLoadHeadSeqNum() 478 { 479 if (loadQueue[loadHead]) { 480 return loadQueue[loadHead]->seqNum; 481 } else { 482 return 0; 483 } 484 485 } 486 487 /** Returns the index of the head store instruction. */ 488 int getStoreHead() { return storeHead; } 489 /** Returns the sequence number of the head store instruction. */ 490 InstSeqNum getStoreHeadSeqNum() 491 { 492 if (storeQueue[storeHead].inst) { 493 return storeQueue[storeHead].inst->seqNum; 494 } else { 495 return 0; 496 } 497 498 } 499 500 /** Returns whether or not the LSQ unit is stalled. */ 501 bool isStalled() { return stalled; } 502}; 503 504template <class Impl> 505template <class T> 506Fault 507LSQUnit<Impl>::read(Request *req, T &data, int load_idx) 508{ 509 DynInstPtr load_inst = loadQueue[load_idx]; 510 511 assert(load_inst); 512 513 assert(!load_inst->isExecuted()); 514 515 // Make sure this isn't an uncacheable access 516 // A bit of a hackish way to get uncached accesses to work only if they're 517 // at the head of the LSQ and are ready to commit (at the head of the ROB 518 // too). 519 if (req->getFlags() & UNCACHEABLE && 520 (load_idx != loadHead || !load_inst->reachedCommit)) { 521 iewStage->rescheduleMemInst(load_inst); 522 return TheISA::genMachineCheckFault(); 523 } 524 525 // Check the SQ for any previous stores that might lead to forwarding 526 int store_idx = load_inst->sqIdx; 527 528 int store_size = 0; 529 530 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, " 531 "storeHead: %i addr: %#x\n", 532 load_idx, store_idx, storeHead, req->getPaddr()); 533 534#if FULL_SYSTEM 535 if (req->getFlags() & LOCKED) { 536 cpu->lockAddr = req->getPaddr(); 537 cpu->lockFlag = true; 538 } 539#endif 540 541 while (store_idx != -1) { 542 // End once we've reached the top of the LSQ 543 if (store_idx == storeWBIdx) { 544 break; 545 } 546 547 // Move the index to one younger 548 if (--store_idx < 0) 549 store_idx += SQEntries; 550 551 assert(storeQueue[store_idx].inst); 552 553 store_size = storeQueue[store_idx].size; 554 555 if (store_size == 0) 556 continue; 557 558 // Check if the store data is within the lower and upper bounds of 559 // addresses that the request needs. 560 bool store_has_lower_limit = 561 req->getVaddr() >= storeQueue[store_idx].inst->effAddr; 562 bool store_has_upper_limit = 563 (req->getVaddr() + req->getSize()) <= 564 (storeQueue[store_idx].inst->effAddr + store_size); 565 bool lower_load_has_store_part = 566 req->getVaddr() < (storeQueue[store_idx].inst->effAddr + 567 store_size); 568 bool upper_load_has_store_part = 569 (req->getVaddr() + req->getSize()) > 570 storeQueue[store_idx].inst->effAddr; 571 572 // If the store's data has all of the data needed, we can forward. 573 if (store_has_lower_limit && store_has_upper_limit) { 574 // Get shift amount for offset into the store's data. 575 int shift_amt = req->getVaddr() & (store_size - 1); 576 // @todo: Magic number, assumes byte addressing 577 shift_amt = shift_amt << 3; 578 579 // Cast this to type T? 580 data = storeQueue[store_idx].data >> shift_amt; 581 582 assert(!load_inst->memData); 583 load_inst->memData = new uint8_t[64]; 584 585 memcpy(load_inst->memData, &data, req->getSize()); 586 587 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to " 588 "addr %#x, data %#x\n", 589 store_idx, req->getVaddr(), data); 590 591 PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast); 592 data_pkt->dataStatic(load_inst->memData); 593 594 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this); 595 596 // We'll say this has a 1 cycle load-store forwarding latency 597 // for now. 598 // @todo: Need to make this a parameter. 599 wb->schedule(curTick); 600 601 // Should keep track of stat for forwarded data 602 return NoFault; 603 } else if ((store_has_lower_limit && lower_load_has_store_part) || 604 (store_has_upper_limit && upper_load_has_store_part) || 605 (lower_load_has_store_part && upper_load_has_store_part)) { 606 // This is the partial store-load forwarding case where a store 607 // has only part of the load's data. 608 609 // If it's already been written back, then don't worry about 610 // stalling on it. 611 if (storeQueue[store_idx].completed) { 612 continue; 613 } 614 615 // Must stall load and force it to retry, so long as it's the oldest 616 // load that needs to do so. 617 if (!stalled || 618 (stalled && 619 load_inst->seqNum < 620 loadQueue[stallingLoadIdx]->seqNum)) { 621 stalled = true; 622 stallingStoreIsn = storeQueue[store_idx].inst->seqNum; 623 stallingLoadIdx = load_idx; 624 } 625 626 // Tell IQ/mem dep unit that this instruction will need to be 627 // rescheduled eventually 628 iewStage->rescheduleMemInst(load_inst); 629 630 // Do not generate a writeback event as this instruction is not 631 // complete. 632 DPRINTF(LSQUnit, "Load-store forwarding mis-match. " 633 "Store idx %i to load addr %#x\n", 634 store_idx, req->getVaddr()); 635 636 return NoFault; 637 } 638 } 639 640 // If there's no forwarding case, then go access memory 641 DPRINTF(LSQUnit, "Doing functional access for inst [sn:%lli] PC %#x\n", 642 load_inst->seqNum, load_inst->readPC()); 643 644 assert(!load_inst->memData); 645 load_inst->memData = new uint8_t[64]; 646 647 ++usedPorts; 648 649 DPRINTF(LSQUnit, "Doing timing access for inst PC %#x\n", 650 load_inst->readPC()); 651 652 PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast); 653 data_pkt->dataStatic(load_inst->memData); 654 655 LSQSenderState *state = new LSQSenderState; 656 state->isLoad = true; 657 state->idx = load_idx; 658 state->inst = load_inst; 659 data_pkt->senderState = state; 660 661 // if we have a cache, do cache access too 662 if (!dcachePort->sendTiming(data_pkt)) { 663 // There's an older load that's already going to squash. 664 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum) 665 return NoFault; 666 667 // Record that the load was blocked due to memory. This 668 // load will squash all instructions after it, be 669 // refetched, and re-executed. 670 isLoadBlocked = true; 671 loadBlockedHandled = false; 672 blockedLoadSeqNum = load_inst->seqNum; 673 // No fault occurred, even though the interface is blocked. 674 return NoFault; 675 } 676 677 if (data_pkt->result != Packet::Success) { 678 DPRINTF(LSQUnit, "LSQUnit: D-cache miss!\n"); 679 DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n", 680 load_inst->seqNum); 681 } else { 682 DPRINTF(LSQUnit, "LSQUnit: D-cache hit!\n"); 683 DPRINTF(Activity, "Activity: ld accessing mem hit [sn:%lli]\n", 684 load_inst->seqNum); 685 } 686 687 return NoFault; 688} 689 690template <class Impl> 691template <class T> 692Fault 693LSQUnit<Impl>::write(Request *req, T &data, int store_idx) 694{ 695 assert(storeQueue[store_idx].inst); 696 697 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x" 698 " | storeHead:%i [sn:%i]\n", 699 store_idx, req->getPaddr(), data, storeHead, 700 storeQueue[store_idx].inst->seqNum); 701 702 storeQueue[store_idx].req = req; 703 storeQueue[store_idx].size = sizeof(T); 704 storeQueue[store_idx].data = data; 705 706 // This function only writes the data to the store queue, so no fault 707 // can happen here. 708 return NoFault; 709} 710 711#endif // __CPU_O3_LSQ_UNIT_HH__
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