lsq_unit.hh (8809:bb10807da889) | lsq_unit.hh (8817:c36441eed919) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 23 unchanged lines hidden (view full) --- 32#ifndef __CPU_O3_LSQ_UNIT_HH__ 33#define __CPU_O3_LSQ_UNIT_HH__ 34 35#include <algorithm> 36#include <cstring> 37#include <map> 38#include <queue> 39 | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 23 unchanged lines hidden (view full) --- 32#ifndef __CPU_O3_LSQ_UNIT_HH__ 33#define __CPU_O3_LSQ_UNIT_HH__ 34 35#include <algorithm> 36#include <cstring> 37#include <map> 38#include <queue> 39 |
40#include "arch/faults.hh" | |
41#include "arch/generic/debugfaults.hh" 42#include "arch/isa_traits.hh" 43#include "arch/locked_mem.hh" 44#include "arch/mmapped_ipr.hh" 45#include "base/fast_alloc.hh" 46#include "base/hashmap.hh" 47#include "config/the_isa.hh" 48#include "cpu/inst_seq.hh" 49#include "cpu/timebuf.hh" 50#include "debug/LSQUnit.hh" 51#include "mem/packet.hh" 52#include "mem/port.hh" | 40#include "arch/generic/debugfaults.hh" 41#include "arch/isa_traits.hh" 42#include "arch/locked_mem.hh" 43#include "arch/mmapped_ipr.hh" 44#include "base/fast_alloc.hh" 45#include "base/hashmap.hh" 46#include "config/the_isa.hh" 47#include "cpu/inst_seq.hh" 48#include "cpu/timebuf.hh" 49#include "debug/LSQUnit.hh" 50#include "mem/packet.hh" 51#include "mem/port.hh" |
52#include "sim/fault_fwd.hh" |
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53 54struct DerivO3CPUParams; 55 56/** 57 * Class that implements the actual LQ and SQ for each specific 58 * thread. Both are circular queues; load entries are freed upon 59 * committing, while store entries are freed once they writeback. The 60 * LSQUnit tracks if there are memory ordering violations, and also --- 860 unchanged lines hidden --- | 53 54struct DerivO3CPUParams; 55 56/** 57 * Class that implements the actual LQ and SQ for each specific 58 * thread. Both are circular queues; load entries are freed upon 59 * committing, while store entries are freed once they writeback. The 60 * LSQUnit tracks if there are memory ordering violations, and also --- 860 unchanged lines hidden --- |