lsq_unit.hh (8591:8f23aeaf6a91) | lsq_unit.hh (8727:b3995530319f) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 439 unchanged lines hidden (view full) --- 448 bool isStoreBlocked; 449 450 /** Whether or not a load is blocked due to the memory system. */ 451 bool isLoadBlocked; 452 453 /** Has the blocked load been handled. */ 454 bool loadBlockedHandled; 455 | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 439 unchanged lines hidden (view full) --- 448 bool isStoreBlocked; 449 450 /** Whether or not a load is blocked due to the memory system. */ 451 bool isLoadBlocked; 452 453 /** Has the blocked load been handled. */ 454 bool loadBlockedHandled; 455 |
456 /** Whether or not a store is in flight. */ 457 bool storeInFlight; 458 |
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456 /** The sequence number of the blocked load. */ 457 InstSeqNum blockedLoadSeqNum; 458 459 /** The oldest load that caused a memory ordering violation. */ 460 DynInstPtr memDepViolator; 461 462 /** Whether or not there is a packet that couldn't be sent because of 463 * a lack of cache ports. */ 464 bool hasPendingPkt; 465 466 /** The packet that is pending free cache ports. */ 467 PacketPtr pendingPkt; 468 | 459 /** The sequence number of the blocked load. */ 460 InstSeqNum blockedLoadSeqNum; 461 462 /** The oldest load that caused a memory ordering violation. */ 463 DynInstPtr memDepViolator; 464 465 /** Whether or not there is a packet that couldn't be sent because of 466 * a lack of cache ports. */ 467 bool hasPendingPkt; 468 469 /** The packet that is pending free cache ports. */ 470 PacketPtr pendingPkt; 471 |
472 /** Flag for memory model. */ 473 bool needsTSO; 474 |
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469 // Will also need how many read/write ports the Dcache has. Or keep track 470 // of that in stage that is one level up, and only call executeLoad/Store 471 // the appropriate number of times. 472 /** Total number of loads forwaded from LSQ stores. */ 473 Stats::Scalar lsqForwLoads; 474 475 /** Total number of loads ignored due to invalid addresses. */ 476 Stats::Scalar invAddrLoads; --- 439 unchanged lines hidden --- | 475 // Will also need how many read/write ports the Dcache has. Or keep track 476 // of that in stage that is one level up, and only call executeLoad/Store 477 // the appropriate number of times. 478 /** Total number of loads forwaded from LSQ stores. */ 479 Stats::Scalar lsqForwLoads; 480 481 /** Total number of loads ignored due to invalid addresses. */ 482 Stats::Scalar invAddrLoads; --- 439 unchanged lines hidden --- |