1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_LSQ_UNIT_HH__
33#define __CPU_O3_LSQ_UNIT_HH__
34
35#include <algorithm>
36#include <map>
37#include <queue>
38
39#include "arch/faults.hh"
40#include "config/full_system.hh"
41#include "base/hashmap.hh"
42#include "cpu/inst_seq.hh"
43#include "mem/packet_impl.hh"
44#include "mem/port.hh"
45
46/**
47 * Class that implements the actual LQ and SQ for each specific
48 * thread. Both are circular queues; load entries are freed upon
49 * committing, while store entries are freed once they writeback. The
50 * LSQUnit tracks if there are memory ordering violations, and also
51 * detects partial load to store forwarding cases (a store only has
52 * part of a load's data) that requires the load to wait until the
53 * store writes back. In the former case it holds onto the instruction
54 * until the dependence unit looks at it, and in the latter it stalls
55 * the LSQ until the store writes back. At that point the load is
56 * replayed.
57 */
58template <class Impl>
59class LSQUnit {
60 protected:
61 typedef TheISA::IntReg IntReg;
62 public:
63 typedef typename Impl::Params Params;
64 typedef typename Impl::O3CPU O3CPU;
65 typedef typename Impl::DynInstPtr DynInstPtr;
66 typedef typename Impl::CPUPol::IEW IEW;
67 typedef typename Impl::CPUPol::IssueStruct IssueStruct;
68
69 public:
70 /** Constructs an LSQ unit. init() must be called prior to use. */
71 LSQUnit();
72
73 /** Initializes the LSQ unit with the specified number of entries. */
74 void init(Params *params, unsigned maxLQEntries,
75 unsigned maxSQEntries, unsigned id);
76
77 /** Returns the name of the LSQ unit. */
78 std::string name() const;
79
80 /** Registers statistics. */
81 void regStats();
82
83 /** Sets the CPU pointer. */
84 void setCPU(O3CPU *cpu_ptr);
85
86 /** Sets the IEW stage pointer. */
87 void setIEW(IEW *iew_ptr)
88 { iewStage = iew_ptr; }
89
90 /** Switches out LSQ unit. */
91 void switchOut();
92
93 /** Takes over from another CPU's thread. */
94 void takeOverFrom();
95
96 /** Returns if the LSQ is switched out. */
97 bool isSwitchedOut() { return switchedOut; }
98
99 /** Ticks the LSQ unit, which in this case only resets the number of
100 * used cache ports.
101 * @todo: Move the number of used ports up to the LSQ level so it can
102 * be shared by all LSQ units.
103 */
104 void tick() { usedPorts = 0; }
105
106 /** Inserts an instruction. */
107 void insert(DynInstPtr &inst);
108 /** Inserts a load instruction. */
109 void insertLoad(DynInstPtr &load_inst);
110 /** Inserts a store instruction. */
111 void insertStore(DynInstPtr &store_inst);
112
113 /** Executes a load instruction. */
114 Fault executeLoad(DynInstPtr &inst);
115
116 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
117 /** Executes a store instruction. */
118 Fault executeStore(DynInstPtr &inst);
119
120 /** Commits the head load. */
121 void commitLoad();
122 /** Commits loads older than a specific sequence number. */
123 void commitLoads(InstSeqNum &youngest_inst);
124
125 /** Commits stores older than a specific sequence number. */
126 void commitStores(InstSeqNum &youngest_inst);
127
128 /** Writes back stores. */
129 void writebackStores();
130
131 /** Completes the data access that has been returned from the
132 * memory system. */
133 void completeDataAccess(PacketPtr pkt);
134
135 /** Clears all the entries in the LQ. */
136 void clearLQ();
137
138 /** Clears all the entries in the SQ. */
139 void clearSQ();
140
141 /** Resizes the LQ to a given size. */
142 void resizeLQ(unsigned size);
143
144 /** Resizes the SQ to a given size. */
145 void resizeSQ(unsigned size);
146
147 /** Squashes all instructions younger than a specific sequence number. */
148 void squash(const InstSeqNum &squashed_num);
149
150 /** Returns if there is a memory ordering violation. Value is reset upon
151 * call to getMemDepViolator().
152 */
153 bool violation() { return memDepViolator; }
154
155 /** Returns the memory ordering violator. */
156 DynInstPtr getMemDepViolator();
157
158 /** Returns if a load became blocked due to the memory system. */
159 bool loadBlocked()
160 { return isLoadBlocked; }
161
162 /** Clears the signal that a load became blocked. */
163 void clearLoadBlocked()
164 { isLoadBlocked = false; }
165
166 /** Returns if the blocked load was handled. */
167 bool isLoadBlockedHandled()
168 { return loadBlockedHandled; }
169
170 /** Records the blocked load as being handled. */
171 void setLoadBlockedHandled()
172 { loadBlockedHandled = true; }
173
174 /** Returns the number of free entries (min of free LQ and SQ entries). */
175 unsigned numFreeEntries();
176
177 /** Returns the number of loads ready to execute. */
178 int numLoadsReady();
179
180 /** Returns the number of loads in the LQ. */
181 int numLoads() { return loads; }
182
183 /** Returns the number of stores in the SQ. */
184 int numStores() { return stores; }
185
186 /** Returns if either the LQ or SQ is full. */
187 bool isFull() { return lqFull() || sqFull(); }
188
189 /** Returns if the LQ is full. */
190 bool lqFull() { return loads >= (LQEntries - 1); }
191
192 /** Returns if the SQ is full. */
193 bool sqFull() { return stores >= (SQEntries - 1); }
194
195 /** Returns the number of instructions in the LSQ. */
196 unsigned getCount() { return loads + stores; }
197
198 /** Returns if there are any stores to writeback. */
199 bool hasStoresToWB() { return storesToWB; }
200
201 /** Returns the number of stores to writeback. */
202 int numStoresToWB() { return storesToWB; }
203
204 /** Returns if the LSQ unit will writeback on this cycle. */
205 bool willWB() { return storeQueue[storeWBIdx].canWB &&
206 !storeQueue[storeWBIdx].completed &&
207 !isStoreBlocked; }
208
209 private:
210 /** Writes back the instruction, sending it to IEW. */
211 void writeback(DynInstPtr &inst, PacketPtr pkt);
212
213 /** Handles completing the send of a store to memory. */
214 void storePostSend(Packet *pkt);
215
216 /** Completes the store at the specified index. */
217 void completeStore(int store_idx);
218
219 /** Handles doing the retry. */
220 void recvRetry();
221
222 /** Increments the given store index (circular queue). */
223 inline void incrStIdx(int &store_idx);
224 /** Decrements the given store index (circular queue). */
225 inline void decrStIdx(int &store_idx);
226 /** Increments the given load index (circular queue). */
227 inline void incrLdIdx(int &load_idx);
228 /** Decrements the given load index (circular queue). */
229 inline void decrLdIdx(int &load_idx);
230
231 public:
232 /** Debugging function to dump instructions in the LSQ. */
233 void dumpInsts();
234
235 private:
236 /** Pointer to the CPU. */
237 O3CPU *cpu;
238
239 /** Pointer to the IEW stage. */
240 IEW *iewStage;
241
242 /** Pointer to memory object. */
243 MemObject *mem;
244
245 /** DcachePort class for this LSQ Unit. Handles doing the
246 * communication with the cache/memory.
247 * @todo: Needs to be moved to the LSQ level and have some sort
248 * of arbitration.
249 */
250 class DcachePort : public Port
251 {
252 protected:
253 /** Pointer to CPU. */
254 O3CPU *cpu;
255 /** Pointer to LSQ. */
256 LSQUnit *lsq;
257
258 public:
259 /** Default constructor. */
260 DcachePort(O3CPU *_cpu, LSQUnit *_lsq)
261 : Port(_lsq->name() + "-dport"), cpu(_cpu), lsq(_lsq)
262 { }
263
264 protected:
265 /** Atomic version of receive. Panics. */
266 virtual Tick recvAtomic(PacketPtr pkt);
267
268 /** Functional version of receive. Panics. */
269 virtual void recvFunctional(PacketPtr pkt);
270
271 /** Receives status change. Other than range changing, panics. */
272 virtual void recvStatusChange(Status status);
273
274 /** Returns the address ranges of this device. */
275 virtual void getDeviceAddressRanges(AddrRangeList &resp,
276 AddrRangeList &snoop)
277 { resp.clear(); snoop.clear(); }
278
279 /** Timing version of receive. Handles writing back and
280 * completing the load or store that has returned from
281 * memory. */
282 virtual bool recvTiming(PacketPtr pkt);
283
284 /** Handles doing a retry of the previous send. */
285 virtual void recvRetry();
286 };
287
288 /** Pointer to the D-cache. */
289 DcachePort *dcachePort;
290
291 /** Derived class to hold any sender state the LSQ needs. */
292 class LSQSenderState : public Packet::SenderState
293 {
294 public:
295 /** Default constructor. */
296 LSQSenderState()
297 : noWB(false)
298 { }
299
300 /** Instruction who initiated the access to memory. */
301 DynInstPtr inst;
302 /** Whether or not it is a load. */
303 bool isLoad;
304 /** The LQ/SQ index of the instruction. */
305 int idx;
306 /** Whether or not the instruction will need to writeback. */
307 bool noWB;
308 };
309
310 /** Writeback event, specifically for when stores forward data to loads. */
311 class WritebackEvent : public Event {
312 public:
313 /** Constructs a writeback event. */
314 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr);
315
316 /** Processes the writeback event. */
317 void process();
318
319 /** Returns the description of this event. */
320 const char *description();
321
322 private:
323 /** Instruction whose results are being written back. */
324 DynInstPtr inst;
325
326 /** The packet that would have been sent to memory. */
327 PacketPtr pkt;
328
329 /** The pointer to the LSQ unit that issued the store. */
330 LSQUnit<Impl> *lsqPtr;
331 };
332
333 public:
334 struct SQEntry {
335 /** Constructs an empty store queue entry. */
336 SQEntry()
337 : inst(NULL), req(NULL), size(0), data(0),
338 canWB(0), committed(0), completed(0)
339 { }
340
341 /** Constructs a store queue entry for a given instruction. */
342 SQEntry(DynInstPtr &_inst)
343 : inst(_inst), req(NULL), size(0), data(0),
344 canWB(0), committed(0), completed(0)
345 { }
346
347 /** The store instruction. */
348 DynInstPtr inst;
349 /** The request for the store. */
350 RequestPtr req;
351 /** The size of the store. */
352 int size;
353 /** The store data. */
354 IntReg data;
355 /** Whether or not the store can writeback. */
356 bool canWB;
357 /** Whether or not the store is committed. */
358 bool committed;
359 /** Whether or not the store is completed. */
360 bool completed;
361 };
362
363 private:
364 /** The LSQUnit thread id. */
365 unsigned lsqID;
366
367 /** The store queue. */
368 std::vector<SQEntry> storeQueue;
369
370 /** The load queue. */
371 std::vector<DynInstPtr> loadQueue;
372
373 /** The number of LQ entries, plus a sentinel entry (circular queue).
374 * @todo: Consider having var that records the true number of LQ entries.
375 */
376 unsigned LQEntries;
377 /** The number of SQ entries, plus a sentinel entry (circular queue).
378 * @todo: Consider having var that records the true number of SQ entries.
379 */
380 unsigned SQEntries;
381
382 /** The number of load instructions in the LQ. */
383 int loads;
384 /** The number of store instructions in the SQ. */
385 int stores;
386 /** The number of store instructions in the SQ waiting to writeback. */
387 int storesToWB;
388
389 /** The index of the head instruction in the LQ. */
390 int loadHead;
391 /** The index of the tail instruction in the LQ. */
392 int loadTail;
393
394 /** The index of the head instruction in the SQ. */
395 int storeHead;
396 /** The index of the first instruction that may be ready to be
397 * written back, and has not yet been written back.
398 */
399 int storeWBIdx;
400 /** The index of the tail instruction in the SQ. */
401 int storeTail;
402
403 /// @todo Consider moving to a more advanced model with write vs read ports
404 /** The number of cache ports available each cycle. */
405 int cachePorts;
406
407 /** The number of used cache ports in this cycle. */
408 int usedPorts;
409
410 /** Is the LSQ switched out. */
411 bool switchedOut;
412
413 //list<InstSeqNum> mshrSeqNums;
414
415 /** Wire to read information from the issue stage time queue. */
416 typename TimeBuffer<IssueStruct>::wire fromIssue;
417
418 /** Whether or not the LSQ is stalled. */
419 bool stalled;
420 /** The store that causes the stall due to partial store to load
421 * forwarding.
422 */
423 InstSeqNum stallingStoreIsn;
424 /** The index of the above store. */
425 int stallingLoadIdx;
426
427 /** The packet that needs to be retried. */
428 PacketPtr retryPkt;
429
430 /** Whehter or not a store is blocked due to the memory system. */
431 bool isStoreBlocked;
432
433 /** Whether or not a load is blocked due to the memory system. */
434 bool isLoadBlocked;
435
436 /** Has the blocked load been handled. */
437 bool loadBlockedHandled;
438
439 /** The sequence number of the blocked load. */
440 InstSeqNum blockedLoadSeqNum;
441
442 /** The oldest load that caused a memory ordering violation. */
443 DynInstPtr memDepViolator;
444
445 // Will also need how many read/write ports the Dcache has. Or keep track
446 // of that in stage that is one level up, and only call executeLoad/Store
447 // the appropriate number of times.
448
449 /** Total number of loads forwaded from LSQ stores. */
450 Stats::Scalar<> lsqForwLoads;
451
452 /** Total number of loads ignored due to invalid addresses. */
453 Stats::Scalar<> invAddrLoads;
454
455 /** Total number of squashed loads. */
456 Stats::Scalar<> lsqSquashedLoads;
457
458 /** Total number of responses from the memory system that are
459 * ignored due to the instruction already being squashed. */
460 Stats::Scalar<> lsqIgnoredResponses;
461
462 /** Total number of squashed stores. */
463 Stats::Scalar<> lsqSquashedStores;
464
465 /** Total number of software prefetches ignored due to invalid addresses. */
466 Stats::Scalar<> invAddrSwpfs;
467
468 /** Ready loads blocked due to partial store-forwarding. */
469 Stats::Scalar<> lsqBlockedLoads;
470
471 /** Number of loads that were rescheduled. */
472 Stats::Scalar<> lsqRescheduledLoads;
473
474 /** Number of times the LSQ is blocked due to the cache. */
475 Stats::Scalar<> lsqCacheBlocked;
476
477 public:
478 /** Executes the load at the given index. */
479 template <class T>
480 Fault read(Request *req, T &data, int load_idx);
481
482 /** Executes the store at the given index. */
483 template <class T>
484 Fault write(Request *req, T &data, int store_idx);
485
486 /** Returns the index of the head load instruction. */
487 int getLoadHead() { return loadHead; }
488 /** Returns the sequence number of the head load instruction. */
489 InstSeqNum getLoadHeadSeqNum()
490 {
491 if (loadQueue[loadHead]) {
492 return loadQueue[loadHead]->seqNum;
493 } else {
494 return 0;
495 }
496
497 }
498
499 /** Returns the index of the head store instruction. */
500 int getStoreHead() { return storeHead; }
501 /** Returns the sequence number of the head store instruction. */
502 InstSeqNum getStoreHeadSeqNum()
503 {
504 if (storeQueue[storeHead].inst) {
505 return storeQueue[storeHead].inst->seqNum;
506 } else {
507 return 0;
508 }
509
510 }
511
512 /** Returns whether or not the LSQ unit is stalled. */
513 bool isStalled() { return stalled; }
514};
515
516template <class Impl>
517template <class T>
518Fault
519LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
520{
521 DynInstPtr load_inst = loadQueue[load_idx];
522
523 assert(load_inst);
524
525 assert(!load_inst->isExecuted());
526
527 // Make sure this isn't an uncacheable access
528 // A bit of a hackish way to get uncached accesses to work only if they're
529 // at the head of the LSQ and are ready to commit (at the head of the ROB
530 // too).
531 if (req->getFlags() & UNCACHEABLE &&
532 (load_idx != loadHead || !load_inst->isAtCommit())) {
533 iewStage->rescheduleMemInst(load_inst);
534 ++lsqRescheduledLoads;
535 return TheISA::genMachineCheckFault();
536 }
537
538 // Check the SQ for any previous stores that might lead to forwarding
539 int store_idx = load_inst->sqIdx;
540
541 int store_size = 0;
542
543 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
544 "storeHead: %i addr: %#x\n",
545 load_idx, store_idx, storeHead, req->getPaddr());
546
547#if FULL_SYSTEM
548 if (req->getFlags() & LOCKED) {
549 cpu->lockAddr = req->getPaddr();
550 cpu->lockFlag = true;
551 }
552#endif
553
554 while (store_idx != -1) {
555 // End once we've reached the top of the LSQ
556 if (store_idx == storeWBIdx) {
557 break;
558 }
559
560 // Move the index to one younger
561 if (--store_idx < 0)
562 store_idx += SQEntries;
563
564 assert(storeQueue[store_idx].inst);
565
566 store_size = storeQueue[store_idx].size;
567
568 if (store_size == 0)
569 continue;
570
571 // Check if the store data is within the lower and upper bounds of
572 // addresses that the request needs.
573 bool store_has_lower_limit =
574 req->getVaddr() >= storeQueue[store_idx].inst->effAddr;
575 bool store_has_upper_limit =
576 (req->getVaddr() + req->getSize()) <=
577 (storeQueue[store_idx].inst->effAddr + store_size);
578 bool lower_load_has_store_part =
579 req->getVaddr() < (storeQueue[store_idx].inst->effAddr +
580 store_size);
581 bool upper_load_has_store_part =
582 (req->getVaddr() + req->getSize()) >
583 storeQueue[store_idx].inst->effAddr;
584
585 // If the store's data has all of the data needed, we can forward.
586 if (store_has_lower_limit && store_has_upper_limit) {
587 // Get shift amount for offset into the store's data.
588 int shift_amt = req->getVaddr() & (store_size - 1);
589 // @todo: Magic number, assumes byte addressing
590 shift_amt = shift_amt << 3;
591
592 // Cast this to type T?
593 data = storeQueue[store_idx].data >> shift_amt;
594
595 assert(!load_inst->memData);
596 load_inst->memData = new uint8_t[64];
597
598 memcpy(load_inst->memData, &data, req->getSize());
599
600 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
601 "addr %#x, data %#x\n",
602 store_idx, req->getVaddr(), data);
603
604 PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
605 data_pkt->dataStatic(load_inst->memData);
606
607 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
608
609 // We'll say this has a 1 cycle load-store forwarding latency
610 // for now.
611 // @todo: Need to make this a parameter.
612 wb->schedule(curTick);
613
614 ++lsqForwLoads;
615 return NoFault;
616 } else if ((store_has_lower_limit && lower_load_has_store_part) ||
617 (store_has_upper_limit && upper_load_has_store_part) ||
618 (lower_load_has_store_part && upper_load_has_store_part)) {
619 // This is the partial store-load forwarding case where a store
620 // has only part of the load's data.
621
622 // If it's already been written back, then don't worry about
623 // stalling on it.
624 if (storeQueue[store_idx].completed) {
625 continue;
626 }
627
628 // Must stall load and force it to retry, so long as it's the oldest
629 // load that needs to do so.
630 if (!stalled ||
631 (stalled &&
632 load_inst->seqNum <
633 loadQueue[stallingLoadIdx]->seqNum)) {
634 stalled = true;
635 stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
636 stallingLoadIdx = load_idx;
637 }
638
639 // Tell IQ/mem dep unit that this instruction will need to be
640 // rescheduled eventually
641 iewStage->rescheduleMemInst(load_inst);
642 ++lsqRescheduledLoads;
643
644 // Do not generate a writeback event as this instruction is not
645 // complete.
646 DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
647 "Store idx %i to load addr %#x\n",
648 store_idx, req->getVaddr());
649
650 ++lsqBlockedLoads;
651 return NoFault;
652 }
653 }
654
655 // If there's no forwarding case, then go access memory
656 DPRINTF(LSQUnit, "Doing functional access for inst [sn:%lli] PC %#x\n",
657 load_inst->seqNum, load_inst->readPC());
658
659 assert(!load_inst->memData);
660 load_inst->memData = new uint8_t[64];
661
662 ++usedPorts;
663
664 DPRINTF(LSQUnit, "Doing timing access for inst PC %#x\n",
665 load_inst->readPC());
666
667 PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
668 data_pkt->dataStatic(load_inst->memData);
669
670 LSQSenderState *state = new LSQSenderState;
671 state->isLoad = true;
672 state->idx = load_idx;
673 state->inst = load_inst;
674 data_pkt->senderState = state;
675
676 // if we have a cache, do cache access too
677 if (!dcachePort->sendTiming(data_pkt)) {
678 ++lsqCacheBlocked;
679 // There's an older load that's already going to squash.
680 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
681 return NoFault;
682
683 // Record that the load was blocked due to memory. This
684 // load will squash all instructions after it, be
685 // refetched, and re-executed.
686 isLoadBlocked = true;
687 loadBlockedHandled = false;
688 blockedLoadSeqNum = load_inst->seqNum;
689 // No fault occurred, even though the interface is blocked.
690 return NoFault;
691 }
692
693 if (data_pkt->result != Packet::Success) {
694 DPRINTF(LSQUnit, "LSQUnit: D-cache miss!\n");
695 DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
696 load_inst->seqNum);
697 } else {
698 DPRINTF(LSQUnit, "LSQUnit: D-cache hit!\n");
699 DPRINTF(Activity, "Activity: ld accessing mem hit [sn:%lli]\n",
700 load_inst->seqNum);
701 }
702
703 return NoFault;
704}
705
706template <class Impl>
707template <class T>
708Fault
709LSQUnit<Impl>::write(Request *req, T &data, int store_idx)
710{
711 assert(storeQueue[store_idx].inst);
712
713 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x"
714 " | storeHead:%i [sn:%i]\n",
715 store_idx, req->getPaddr(), data, storeHead,
716 storeQueue[store_idx].inst->seqNum);
717
718 storeQueue[store_idx].req = req;
719 storeQueue[store_idx].size = sizeof(T);
720 storeQueue[store_idx].data = data;
721
722 // This function only writes the data to the store queue, so no fault
723 // can happen here.
724 return NoFault;
725}
726
727#endif // __CPU_O3_LSQ_UNIT_HH__