1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_O3_LSQ_UNIT_HH__
30#define __CPU_O3_LSQ_UNIT_HH__
31
32#include <algorithm>
33#include <map>
34#include <queue>
35
36#include "arch/faults.hh"
37#include "config/full_system.hh"
38#include "base/hashmap.hh"
39#include "cpu/inst_seq.hh"
40#include "mem/packet.hh"
41#include "mem/port.hh"
42//#include "mem/page_table.hh"
43//#include "sim/debug.hh"
44//#include "sim/sim_object.hh"
45
46/**
47 * Class that implements the actual LQ and SQ for each specific
48 * thread. Both are circular queues; load entries are freed upon
49 * committing, while store entries are freed once they writeback. The
50 * LSQUnit tracks if there are memory ordering violations, and also
51 * detects partial load to store forwarding cases (a store only has
52 * part of a load's data) that requires the load to wait until the
53 * store writes back. In the former case it holds onto the instruction
54 * until the dependence unit looks at it, and in the latter it stalls
55 * the LSQ until the store writes back. At that point the load is
56 * replayed.
57 */
58template <class Impl>
59class LSQUnit {
60 protected:
61 typedef TheISA::IntReg IntReg;
62 public:
63 typedef typename Impl::Params Params;
64 typedef typename Impl::FullCPU FullCPU;
65 typedef typename Impl::DynInstPtr DynInstPtr;
66 typedef typename Impl::CPUPol::IEW IEW;
67 typedef typename Impl::CPUPol::IssueStruct IssueStruct;
68
69 public:
70 /** Constructs an LSQ unit. init() must be called prior to use. */
71 LSQUnit();
72
73 /** Initializes the LSQ unit with the specified number of entries. */
74 void init(Params *params, unsigned maxLQEntries,
75 unsigned maxSQEntries, unsigned id);
76
77 /** Returns the name of the LSQ unit. */
78 std::string name() const;
79
80 /** Sets the CPU pointer. */
81 void setCPU(FullCPU *cpu_ptr);
82
83 /** Sets the IEW stage pointer. */
84 void setIEW(IEW *iew_ptr)
85 { iewStage = iew_ptr; }
86
87 /** Sets the page table pointer. */
88// void setPageTable(PageTable *pt_ptr);
89
90 /** Switches out LSQ unit. */
91 void switchOut();
92
93 /** Takes over from another CPU's thread. */
94 void takeOverFrom();
95
96 /** Returns if the LSQ is switched out. */
97 bool isSwitchedOut() { return switchedOut; }
98
99 /** Ticks the LSQ unit, which in this case only resets the number of
100 * used cache ports.
101 * @todo: Move the number of used ports up to the LSQ level so it can
102 * be shared by all LSQ units.
103 */
104 void tick() { usedPorts = 0; }
105
106 /** Inserts an instruction. */
107 void insert(DynInstPtr &inst);
108 /** Inserts a load instruction. */
109 void insertLoad(DynInstPtr &load_inst);
110 /** Inserts a store instruction. */
111 void insertStore(DynInstPtr &store_inst);
112
113 /** Executes a load instruction. */
114 Fault executeLoad(DynInstPtr &inst);
115
116 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
117 /** Executes a store instruction. */
118 Fault executeStore(DynInstPtr &inst);
119
120 /** Commits the head load. */
121 void commitLoad();
122 /** Commits loads older than a specific sequence number. */
123 void commitLoads(InstSeqNum &youngest_inst);
124
125 /** Commits stores older than a specific sequence number. */
126 void commitStores(InstSeqNum &youngest_inst);
127
128 /** Writes back stores. */
129 void writebackStores();
130
131 void completeDataAccess(PacketPtr pkt);
132
133 void completeStoreDataAccess(DynInstPtr &inst);
134
135 // @todo: Include stats in the LSQ unit.
136 //void regStats();
137
138 /** Clears all the entries in the LQ. */
139 void clearLQ();
140
141 /** Clears all the entries in the SQ. */
142 void clearSQ();
143
144 /** Resizes the LQ to a given size. */
145 void resizeLQ(unsigned size);
146
147 /** Resizes the SQ to a given size. */
148 void resizeSQ(unsigned size);
149
150 /** Squashes all instructions younger than a specific sequence number. */
151 void squash(const InstSeqNum &squashed_num);
152
153 /** Returns if there is a memory ordering violation. Value is reset upon
154 * call to getMemDepViolator().
155 */
156 bool violation() { return memDepViolator; }
157
158 /** Returns the memory ordering violator. */
159 DynInstPtr getMemDepViolator();
160
161 /** Returns if a load became blocked due to the memory system. */
162 bool loadBlocked()
163 { return isLoadBlocked; }
164
165 /** Clears the signal that a load became blocked. */
166 void clearLoadBlocked()
167 { isLoadBlocked = false; }
168
169 /** Returns if the blocked load was handled. */
170 bool isLoadBlockedHandled()
171 { return loadBlockedHandled; }
172
173 /** Records the blocked load as being handled. */
174 void setLoadBlockedHandled()
175 { loadBlockedHandled = true; }
176
177 /** Returns the number of free entries (min of free LQ and SQ entries). */
178 unsigned numFreeEntries();
179
180 /** Returns the number of loads ready to execute. */
181 int numLoadsReady();
182
183 /** Returns the number of loads in the LQ. */
184 int numLoads() { return loads; }
185
186 /** Returns the number of stores in the SQ. */
187 int numStores() { return stores; }
188
189 /** Returns if either the LQ or SQ is full. */
190 bool isFull() { return lqFull() || sqFull(); }
191
192 /** Returns if the LQ is full. */
193 bool lqFull() { return loads >= (LQEntries - 1); }
194
195 /** Returns if the SQ is full. */
196 bool sqFull() { return stores >= (SQEntries - 1); }
197
198 /** Returns the number of instructions in the LSQ. */
199 unsigned getCount() { return loads + stores; }
200
201 /** Returns if there are any stores to writeback. */
202 bool hasStoresToWB() { return storesToWB; }
203
204 /** Returns the number of stores to writeback. */
205 int numStoresToWB() { return storesToWB; }
206
207 /** Returns if the LSQ unit will writeback on this cycle. */
208 bool willWB() { return storeQueue[storeWBIdx].canWB &&
209 !storeQueue[storeWBIdx].completed/* &&
210 !dcacheInterface->isBlocked()*/; }
211
212 private:
213 /** Completes the store at the specified index. */
214 void completeStore(int store_idx);
215
216 /** Increments the given store index (circular queue). */
217 inline void incrStIdx(int &store_idx);
218 /** Decrements the given store index (circular queue). */
219 inline void decrStIdx(int &store_idx);
220 /** Increments the given load index (circular queue). */
221 inline void incrLdIdx(int &load_idx);
222 /** Decrements the given load index (circular queue). */
223 inline void decrLdIdx(int &load_idx);
224
225 public:
226 /** Debugging function to dump instructions in the LSQ. */
227 void dumpInsts();
228
229 private:
230 /** Pointer to the CPU. */
231 FullCPU *cpu;
232
233 /** Pointer to the IEW stage. */
234 IEW *iewStage;
235
236 MemObject *mem;
237
238 class DcachePort : public Port
239 {
240 protected:
241 FullCPU *cpu;
242 LSQUnit *lsq;
243
244 public:
245 DcachePort(FullCPU *_cpu, LSQUnit *_lsq)
246 : Port(_lsq->name() + "-dport"), cpu(_cpu), lsq(_lsq)
247 { }
248
249 protected:
250 virtual Tick recvAtomic(PacketPtr pkt);
251
252 virtual void recvFunctional(PacketPtr pkt);
253
254 virtual void recvStatusChange(Status status);
255
256 virtual void getDeviceAddressRanges(AddrRangeList &resp,
257 AddrRangeList &snoop)
258 { resp.clear(); snoop.clear(); }
259
260 virtual bool recvTiming(PacketPtr pkt);
261
262 virtual void recvRetry();
263 };
264
265 /** Pointer to the D-cache. */
266 DcachePort *dcachePort;
267
268 /** Pointer to the page table. */
269// PageTable *pTable;
270
271 public:
272 struct SQEntry {
273 /** Constructs an empty store queue entry. */
274 SQEntry()
275 : inst(NULL), req(NULL), size(0), data(0),
276 canWB(0), committed(0), completed(0)
277 { }
278
279 /** Constructs a store queue entry for a given instruction. */
280 SQEntry(DynInstPtr &_inst)
281 : inst(_inst), req(NULL), size(0), data(0),
282 canWB(0), committed(0), completed(0)
283 { }
284
285 /** The store instruction. */
286 DynInstPtr inst;
287 /** The request for the store. */
288 RequestPtr req;
289 /** The size of the store. */
290 int size;
291 /** The store data. */
292 IntReg data;
293 /** Whether or not the store can writeback. */
294 bool canWB;
295 /** Whether or not the store is committed. */
296 bool committed;
297 /** Whether or not the store is completed. */
298 bool completed;
299 };
300
301 private:
302 /** The LSQUnit thread id. */
303 unsigned lsqID;
304
305 /** The store queue. */
306 std::vector<SQEntry> storeQueue;
307
308 /** The load queue. */
309 std::vector<DynInstPtr> loadQueue;
310
311 /** The number of LQ entries, plus a sentinel entry (circular queue).
312 * @todo: Consider having var that records the true number of LQ entries.
313 */
314 unsigned LQEntries;
315 /** The number of SQ entries, plus a sentinel entry (circular queue).
316 * @todo: Consider having var that records the true number of SQ entries.
317 */
318 unsigned SQEntries;
319
320 /** The number of load instructions in the LQ. */
321 int loads;
322 /** The number of store instructions in the SQ. */
323 int stores;
324 /** The number of store instructions in the SQ waiting to writeback. */
325 int storesToWB;
326
327 /** The index of the head instruction in the LQ. */
328 int loadHead;
329 /** The index of the tail instruction in the LQ. */
330 int loadTail;
331
332 /** The index of the head instruction in the SQ. */
333 int storeHead;
334 /** The index of the first instruction that may be ready to be
335 * written back, and has not yet been written back.
336 */
337 int storeWBIdx;
338 /** The index of the tail instruction in the SQ. */
339 int storeTail;
340
341 /// @todo Consider moving to a more advanced model with write vs read ports
342 /** The number of cache ports available each cycle. */
343 int cachePorts;
344
345 /** The number of used cache ports in this cycle. */
346 int usedPorts;
347
348 /** Is the LSQ switched out. */
349 bool switchedOut;
350
351 //list<InstSeqNum> mshrSeqNums;
352
353 /** Wire to read information from the issue stage time queue. */
354 typename TimeBuffer<IssueStruct>::wire fromIssue;
355
356 /** Whether or not the LSQ is stalled. */
357 bool stalled;
358 /** The store that causes the stall due to partial store to load
359 * forwarding.
360 */
361 InstSeqNum stallingStoreIsn;
362 /** The index of the above store. */
363 int stallingLoadIdx;
364
365 /** Whether or not a load is blocked due to the memory system. */
366 bool isLoadBlocked;
367
368 /** Has the blocked load been handled. */
369 bool loadBlockedHandled;
370
371 /** The sequence number of the blocked load. */
372 InstSeqNum blockedLoadSeqNum;
373
374 /** The oldest load that caused a memory ordering violation. */
375 DynInstPtr memDepViolator;
376
377 // Will also need how many read/write ports the Dcache has. Or keep track
378 // of that in stage that is one level up, and only call executeLoad/Store
379 // the appropriate number of times.
380/*
381 // total number of loads forwaded from LSQ stores
382 Stats::Vector<> lsq_forw_loads;
383
384 // total number of loads ignored due to invalid addresses
385 Stats::Vector<> inv_addr_loads;
386
387 // total number of software prefetches ignored due to invalid addresses
388 Stats::Vector<> inv_addr_swpfs;
389
390 // total non-speculative bogus addresses seen (debug var)
391 Counter sim_invalid_addrs;
392 Stats::Vector<> fu_busy; //cumulative fu busy
393
394 // ready loads blocked due to memory disambiguation
395 Stats::Vector<> lsq_blocked_loads;
396
397 Stats::Scalar<> lsqInversion;
398*/
399 public:
400 /** Executes the load at the given index. */
401 template <class T>
402 Fault read(Request *req, T &data, int load_idx);
403
404 /** Executes the store at the given index. */
405 template <class T>
406 Fault write(Request *req, T &data, int store_idx);
407
408 /** Returns the index of the head load instruction. */
409 int getLoadHead() { return loadHead; }
410 /** Returns the sequence number of the head load instruction. */
411 InstSeqNum getLoadHeadSeqNum()
412 {
413 if (loadQueue[loadHead]) {
414 return loadQueue[loadHead]->seqNum;
415 } else {
416 return 0;
417 }
418
419 }
420
421 /** Returns the index of the head store instruction. */
422 int getStoreHead() { return storeHead; }
423 /** Returns the sequence number of the head store instruction. */
424 InstSeqNum getStoreHeadSeqNum()
425 {
426 if (storeQueue[storeHead].inst) {
427 return storeQueue[storeHead].inst->seqNum;
428 } else {
429 return 0;
430 }
431
432 }
433
434 /** Returns whether or not the LSQ unit is stalled. */
435 bool isStalled() { return stalled; }
436};
437
438template <class Impl>
439template <class T>
440Fault
441LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
442{
443 DynInstPtr load_inst = loadQueue[load_idx];
444
445 assert(load_inst);
446
447 assert(!load_inst->isExecuted());
448
449 // Make sure this isn't an uncacheable access
450 // A bit of a hackish way to get uncached accesses to work only if they're
451 // at the head of the LSQ and are ready to commit (at the head of the ROB
452 // too).
453 if (req->getFlags() & UNCACHEABLE &&
454 (load_idx != loadHead || !load_inst->reachedCommit)) {
455 iewStage->rescheduleMemInst(load_inst);
456 return TheISA::genMachineCheckFault();
457 }
458
459 // Check the SQ for any previous stores that might lead to forwarding
460 int store_idx = load_inst->sqIdx;
461
462 int store_size = 0;
463
464 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
465 "storeHead: %i addr: %#x\n",
466 load_idx, store_idx, storeHead, req->getPaddr());
467
468#if 0
469 if (req->getFlags() & LOCKED) {
470 cpu->lockAddr = req->getPaddr();
471 cpu->lockFlag = true;
472 }
473#endif
474
475 while (store_idx != -1) {
476 // End once we've reached the top of the LSQ
477 if (store_idx == storeWBIdx) {
478 break;
479 }
480
481 // Move the index to one younger
482 if (--store_idx < 0)
483 store_idx += SQEntries;
484
485 assert(storeQueue[store_idx].inst);
486
487 store_size = storeQueue[store_idx].size;
488
489 if (store_size == 0)
490 continue;
491
492 // Check if the store data is within the lower and upper bounds of
493 // addresses that the request needs.
494 bool store_has_lower_limit =
495 req->getVaddr() >= storeQueue[store_idx].inst->effAddr;
496 bool store_has_upper_limit =
497 (req->getVaddr() + req->getSize()) <=
498 (storeQueue[store_idx].inst->effAddr + store_size);
499 bool lower_load_has_store_part =
500 req->getVaddr() < (storeQueue[store_idx].inst->effAddr +
501 store_size);
502 bool upper_load_has_store_part =
503 (req->getVaddr() + req->getSize()) >
504 storeQueue[store_idx].inst->effAddr;
505
506 // If the store's data has all of the data needed, we can forward.
507 if (store_has_lower_limit && store_has_upper_limit) {
508 // Get shift amount for offset into the store's data.
509 int shift_amt = req->getVaddr() & (store_size - 1);
510 // @todo: Magic number, assumes byte addressing
511 shift_amt = shift_amt << 3;
512
513 // Cast this to type T?
514 data = storeQueue[store_idx].data >> shift_amt;
515
516 assert(!load_inst->memData);
517 load_inst->memData = new uint8_t[64];
518
519 memcpy(load_inst->memData, &data, req->getSize());
520
521 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
522 "addr %#x, data %#x\n",
523 store_idx, req->getVaddr(), *(load_inst->memData));
524/*
525 typename LdWritebackEvent *wb =
526 new typename LdWritebackEvent(load_inst,
527 iewStage);
528
529 // We'll say this has a 1 cycle load-store forwarding latency
530 // for now.
531 // @todo: Need to make this a parameter.
532 wb->schedule(curTick);
533*/
534 // Should keep track of stat for forwarded data
535 return NoFault;
536 } else if ((store_has_lower_limit && lower_load_has_store_part) ||
537 (store_has_upper_limit && upper_load_has_store_part) ||
538 (lower_load_has_store_part && upper_load_has_store_part)) {
539 // This is the partial store-load forwarding case where a store
540 // has only part of the load's data.
541
542 // If it's already been written back, then don't worry about
543 // stalling on it.
544 if (storeQueue[store_idx].completed) {
545 continue;
546 }
547
548 // Must stall load and force it to retry, so long as it's the oldest
549 // load that needs to do so.
550 if (!stalled ||
551 (stalled &&
552 load_inst->seqNum <
553 loadQueue[stallingLoadIdx]->seqNum)) {
554 stalled = true;
555 stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
556 stallingLoadIdx = load_idx;
557 }
558
559 // Tell IQ/mem dep unit that this instruction will need to be
560 // rescheduled eventually
561 iewStage->rescheduleMemInst(load_inst);
562
563 // Do not generate a writeback event as this instruction is not
564 // complete.
565 DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
566 "Store idx %i to load addr %#x\n",
567 store_idx, req->getVaddr());
568
569 return NoFault;
570 }
571 }
572
573 // If there's no forwarding case, then go access memory
574 DPRINTF(LSQUnit, "Doing functional access for inst [sn:%lli] PC %#x\n",
575 load_inst->seqNum, load_inst->readPC());
576
577 assert(!load_inst->memData);
578 load_inst->memData = new uint8_t[64];
579
580 ++usedPorts;
581
582 DPRINTF(LSQUnit, "Doing timing access for inst PC %#x\n",
583 load_inst->readPC());
584
585 PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
586 data_pkt->dataStatic(load_inst->memData);
587
588 // if we have a cache, do cache access too
589 if (!dcachePort->sendTiming(data_pkt)) {
590 // There's an older load that's already going to squash.
591 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
592 return NoFault;
593
594 // Record that the load was blocked due to memory. This
595 // load will squash all instructions after it, be
596 // refetched, and re-executed.
597 isLoadBlocked = true;
598 loadBlockedHandled = false;
599 blockedLoadSeqNum = load_inst->seqNum;
600 // No fault occurred, even though the interface is blocked.
601 return NoFault;
602 }
603
604 if (data_pkt->result != Packet::Success) {
605 DPRINTF(LSQUnit, "LSQUnit: D-cache miss!\n");
606 DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
607 load_inst->seqNum);
608 } else {
609 DPRINTF(LSQUnit, "LSQUnit: D-cache hit!\n");
610 DPRINTF(Activity, "Activity: ld accessing mem hit [sn:%lli]\n",
611 load_inst->seqNum);
612 }
613
614 return NoFault;
615}
616
617template <class Impl>
618template <class T>
619Fault
620LSQUnit<Impl>::write(Request *req, T &data, int store_idx)
621{
622 assert(storeQueue[store_idx].inst);
623
624 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x"
625 " | storeHead:%i [sn:%i]\n",
626 store_idx, req->getPaddr(), data, storeHead,
627 storeQueue[store_idx].inst->seqNum);
628
629 storeQueue[store_idx].req = req;
630 storeQueue[store_idx].size = sizeof(T);
631 storeQueue[store_idx].data = data;
632
633 // This function only writes the data to the store queue, so no fault
634 // can happen here.
635 return NoFault;
636}
637
638#endif // __CPU_O3_LSQ_UNIT_HH__