1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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356 ~SQEntry()
357 {
358 inst = NULL;
359 }
360
361 /** Constructs a store queue entry for a given instruction. */
362 SQEntry(DynInstPtr &_inst)
363 : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0),
364 isSplit(0), canWB(0), committed(0), completed(0)
365 {
366 std::memset(data, 0, sizeof(data));
367 }
368 /** The store data. */
369 char data[16];
370 /** The store instruction. */
371 DynInstPtr inst;
372 /** The request for the store. */

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379 /** Whether or not the store is split into two requests. */
380 bool isSplit;
381 /** Whether or not the store can writeback. */
382 bool canWB;
383 /** Whether or not the store is committed. */
384 bool committed;
385 /** Whether or not the store is completed. */
386 bool completed;
387 };
388
389 private:
390 /** The LSQUnit thread id. */
391 ThreadID lsqID;
392
393 /** The store queue. */
394 std::vector<SQEntry> storeQueue;

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686 (req->getVaddr() + req->getSize()) >
687 storeQueue[store_idx].inst->effAddr;
688
689 // If the store's data has all of the data needed, we can forward.
690 if ((store_has_lower_limit && store_has_upper_limit)) {
691 // Get shift amount for offset into the store's data.
692 int shift_amt = req->getVaddr() - storeQueue[store_idx].inst->effAddr;
693
694 memcpy(data, storeQueue[store_idx].data + shift_amt,
695 req->getSize());
696
697 assert(!load_inst->memData);
698 load_inst->memData = new uint8_t[64];
699
700 memcpy(load_inst->memData,
701 storeQueue[store_idx].data + shift_amt, req->getSize());
702
703 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
704 "addr %#x, data %#x\n",
705 store_idx, req->getVaddr(), data);
706
707 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
708 data_pkt->dataStatic(load_inst->memData);

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772 }
773 }
774
775 // If there's no forwarding case, then go access memory
776 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %s\n",
777 load_inst->seqNum, load_inst->pcState());
778
779 assert(!load_inst->memData);
780 load_inst->memData = new uint8_t[64];
781
782 ++usedPorts;
783
784 // if we the cache is not blocked, do cache access
785 bool completedFirst = false;
786 if (!lsq->cacheBlocked()) {
787 MemCmd command =
788 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq;

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911 store_idx, req->getPaddr(), data, storeHead,
912 storeQueue[store_idx].inst->seqNum);
913
914 storeQueue[store_idx].req = req;
915 storeQueue[store_idx].sreqLow = sreqLow;
916 storeQueue[store_idx].sreqHigh = sreqHigh;
917 unsigned size = req->getSize();
918 storeQueue[store_idx].size = size;
919 assert(size <= sizeof(storeQueue[store_idx].data));
920
921 // Split stores can only occur in ISAs with unaligned memory accesses. If
922 // a store request has been split, sreqLow and sreqHigh will be non-null.
923 if (TheISA::HasUnalignedMemAcc && sreqLow) {
924 storeQueue[store_idx].isSplit = true;
925 }
926
927 memcpy(storeQueue[store_idx].data, data, size);
928
929 // This function only writes the data to the store queue, so no fault
930 // can happen here.
931 return NoFault;
932}
933
934#endif // __CPU_O3_LSQ_UNIT_HH__