1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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106
107 /** Inserts an instruction. */
108 void insert(DynInstPtr &inst);
109 /** Inserts a load instruction. */
110 void insertLoad(DynInstPtr &load_inst);
111 /** Inserts a store instruction. */
112 void insertStore(DynInstPtr &store_inst);
113
114 /** Executes a load instruction. */
115 Fault executeLoad(DynInstPtr &inst);
116
117 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
118 /** Executes a store instruction. */
119 Fault executeStore(DynInstPtr &inst);
120
121 /** Commits the head load. */

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361 * @todo: Consider having var that records the true number of LQ entries.
362 */
363 unsigned LQEntries;
364 /** The number of SQ entries, plus a sentinel entry (circular queue).
365 * @todo: Consider having var that records the true number of SQ entries.
366 */
367 unsigned SQEntries;
368
369 /** The number of load instructions in the LQ. */
370 int loads;
371 /** The number of store instructions in the SQ. */
372 int stores;
373 /** The number of store instructions in the SQ waiting to writeback. */
374 int storesToWB;
375
376 /** The index of the head instruction in the LQ. */

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