1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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208 /** Returns if the LSQ unit will writeback on this cycle. */
209 bool willWB() { return storeQueue[storeWBIdx].canWB &&
210 !storeQueue[storeWBIdx].completed &&
211 !isStoreBlocked; }
212
213 private:
214 void writeback(DynInstPtr &inst, PacketPtr pkt);
215
216 /** Completes the store at the specified index. */
217 void completeStore(int store_idx);
218
219 /** Increments the given store index (circular queue). */
220 inline void incrStIdx(int &store_idx);
221 /** Decrements the given store index (circular queue). */
222 inline void decrStIdx(int &store_idx);
223 /** Increments the given load index (circular queue). */
224 inline void incrLdIdx(int &load_idx);
225 /** Decrements the given load index (circular queue). */
226 inline void decrLdIdx(int &load_idx);

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394 bool stalled;
395 /** The store that causes the stall due to partial store to load
396 * forwarding.
397 */
398 InstSeqNum stallingStoreIsn;
399 /** The index of the above store. */
400 int stallingLoadIdx;
401
402 bool isStoreBlocked;
403
404 /** Whether or not a load is blocked due to the memory system. */
405 bool isLoadBlocked;
406
407 /** Has the blocked load been handled. */
408 bool loadBlockedHandled;
409

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499 int store_idx = load_inst->sqIdx;
500
501 int store_size = 0;
502
503 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
504 "storeHead: %i addr: %#x\n",
505 load_idx, store_idx, storeHead, req->getPaddr());
506
507#if 0
508 if (req->getFlags() & LOCKED) {
509 cpu->lockAddr = req->getPaddr();
510 cpu->lockFlag = true;
511 }
512#endif
513
514 while (store_idx != -1) {
515 // End once we've reached the top of the LSQ

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554
555 assert(!load_inst->memData);
556 load_inst->memData = new uint8_t[64];
557
558 memcpy(load_inst->memData, &data, req->getSize());
559
560 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
561 "addr %#x, data %#x\n",
562 store_idx, req->getVaddr(), *(load_inst->memData));
563
564 PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
565 data_pkt->dataStatic(load_inst->memData);
566
567 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
568
569 // We'll say this has a 1 cycle load-store forwarding latency
570 // for now.

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