1/*
2 * Copyright (c) 2012-2014,2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46#define __CPU_O3_LSQ_UNIT_HH__
47
48#include <algorithm>
49#include <cstring>
50#include <map>
51#include <queue>
52
53#include "arch/generic/debugfaults.hh"
54#include "arch/isa_traits.hh"
55#include "arch/locked_mem.hh"
56#include "arch/mmapped_ipr.hh"
57#include "config/the_isa.hh"
58#include "cpu/inst_seq.hh"
59#include "cpu/timebuf.hh"
60#include "debug/LSQUnit.hh"
61#include "mem/packet.hh"

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75 * until the dependence unit looks at it, and in the latter it stalls
76 * the LSQ until the store writes back. At that point the load is
77 * replayed.
78 */
79template <class Impl>
80class LSQUnit
81{
82 public:
83 typedef typename Impl::O3CPU O3CPU;
84 typedef typename Impl::DynInstPtr DynInstPtr;
85 typedef typename Impl::CPUPol::IEW IEW;
86 typedef typename Impl::CPUPol::LSQ LSQ;
87 typedef typename Impl::CPUPol::IssueStruct IssueStruct;
88
89 using LSQSenderState = typename LSQ::LSQSenderState;
90 using LSQRequest = typename Impl::CPUPol::LSQ::LSQRequest;
91 private:
92 class LSQEntry
93 {
94 private:
95 /** The instruction. */
96 DynInstPtr inst;
97 /** The request. */
98 LSQRequest* req;
99 /** The size of the operation. */
100 uint8_t _size;
101 /** Valid entry. */
102 bool _valid;
103 public:
104 /** Constructs an empty store queue entry. */
105 LSQEntry()
106 : inst(nullptr), req(nullptr), _size(0), _valid(false)
107 {
108 }

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137 _size = 0;
138 }
139 LSQRequest* request() { return req; }
140 void setRequest(LSQRequest* r) { req = r; }
141 bool hasRequest() { return req != nullptr; }
142 /** Member accessors. */
143 /** @{ */
144 bool valid() const { return _valid; }
145 uint8_t& size() { return _size; }
146 const uint8_t& size() const { return _size; }
147 const DynInstPtr& instruction() const { return inst; }
148 /** @} */
149 };
150
151 class SQEntry : public LSQEntry
152 {
153 private:
154 /** The store data. */
155 char _data[64]; // TODO: 64 should become a parameter
156 /** Whether or not the store can writeback. */
157 bool _canWB;
158 /** Whether or not the store is committed. */
159 bool _committed;
160 /** Whether or not the store is completed. */
161 bool _completed;
162 /** Does this request write all zeros and thus doesn't
163 * have any data attached to it. Used for cache block zero

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654 // desired behavior when handling store conditionals.
655 load_inst->recordResult(false);
656 TheISA::handleLockedRead(load_inst.get(), req->mainRequest());
657 load_inst->recordResult(true);
658 }
659
660 if (req->mainRequest()->isMmappedIpr()) {
661 assert(!load_inst->memData);
662 load_inst->memData = new uint8_t[64];
663
664 ThreadContext *thread = cpu->tcBase(lsqID);
665 PacketPtr main_pkt = new Packet(req->mainRequest(), MemCmd::ReadReq);
666
667 Cycles delay = req->handleIprRead(thread, main_pkt);
668
669 WritebackEvent *wb = new WritebackEvent(load_inst, main_pkt, this);
670 cpu->schedule(wb, cpu->clockEdge(delay));

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