1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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275 MasterPort *dcachePort;
276
277 /** Derived class to hold any sender state the LSQ needs. */
278 class LSQSenderState : public Packet::SenderState
279 {
280 public:
281 /** Default constructor. */
282 LSQSenderState()
283 : mainPkt(NULL), pendingPacket(NULL), outstanding(1),
284 noWB(false), isSplit(false), pktToSend(false), cacheBlocked(false)
285 { }
286
287 /** Instruction who initiated the access to memory. */
288 DynInstPtr inst;
289 /** The main packet from a split load, used during writeback. */
290 PacketPtr mainPkt;
291 /** A second packet from a split store that needs sending. */
292 PacketPtr pendingPacket;

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