1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_LSQ_UNIT_HH__
33#define __CPU_O3_LSQ_UNIT_HH__
34
35#include <algorithm>
36#include <cstring>
37#include <map>
38#include <queue>
39
40#include "arch/faults.hh"
41#include "arch/locked_mem.hh"
42#include "config/full_system.hh"
43#include "base/hashmap.hh"
44#include "cpu/inst_seq.hh"

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288
289 public:
290 struct SQEntry {
291 /** Constructs an empty store queue entry. */
292 SQEntry()
293 : inst(NULL), req(NULL), size(0),
294 canWB(0), committed(0), completed(0)
295 {
296 std::memset(data, 0, sizeof(data));
297 }
298
299 /** Constructs a store queue entry for a given instruction. */
300 SQEntry(DynInstPtr &_inst)
301 : inst(_inst), req(NULL), size(0),
302 canWB(0), committed(0), completed(0)
303 {
304 std::memset(data, 0, sizeof(data));
305 }
306
307 /** The store instruction. */
308 DynInstPtr inst;
309 /** The request for the store. */
310 RequestPtr req;
311 /** The size of the store. */
312 int size;

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