1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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284 /** The pointer to the LSQ unit that issued the store. */
285 LSQUnit<Impl> *lsqPtr;
286 };
287
288 public:
289 struct SQEntry {
290 /** Constructs an empty store queue entry. */
291 SQEntry()
292 : inst(NULL), req(NULL), size(0),
293 canWB(0), committed(0), completed(0)
294 {
295 bzero(data, sizeof(data));
296 }
297
298 /** Constructs a store queue entry for a given instruction. */
299 SQEntry(DynInstPtr &_inst)
300 : inst(_inst), req(NULL), size(0),
301 canWB(0), committed(0), completed(0)
302 {
303 bzero(data, sizeof(data));
304 }
305
306 /** The store instruction. */
307 DynInstPtr inst;
308 /** The request for the store. */
309 RequestPtr req;
310 /** The size of the store. */
311 int size;
312 /** The store data. */
313 char data[sizeof(IntReg)];
314 /** Whether or not the store can writeback. */
315 bool canWB;
316 /** Whether or not the store is committed. */
317 bool committed;
318 /** Whether or not the store is completed. */
319 bool completed;
320 };
321

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553 bool upper_load_has_store_part =
554 (req->getVaddr() + req->getSize()) >
555 storeQueue[store_idx].inst->effAddr;
556
557 // If the store's data has all of the data needed, we can forward.
558 if ((store_has_lower_limit && store_has_upper_limit)) {
559 // Get shift amount for offset into the store's data.
560 int shift_amt = req->getVaddr() & (store_size - 1);
561
562 memcpy(&data, storeQueue[store_idx].data + shift_amt, sizeof(T));
563
564 assert(!load_inst->memData);
565 load_inst->memData = new uint8_t[64];
566
567 memcpy(load_inst->memData,
568 storeQueue[store_idx].data + shift_amt, req->getSize());
569
570 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
571 "addr %#x, data %#x\n",
572 store_idx, req->getVaddr(), data);
573
574 PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq,
575 Packet::Broadcast);
576 data_pkt->dataStatic(load_inst->memData);

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707
708 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x"
709 " | storeHead:%i [sn:%i]\n",
710 store_idx, req->getPaddr(), data, storeHead,
711 storeQueue[store_idx].inst->seqNum);
712
713 storeQueue[store_idx].req = req;
714 storeQueue[store_idx].size = sizeof(T);
715 assert(sizeof(T) <= sizeof(storeQueue[store_idx].data));
716
717 T gData = htog(data);
718 memcpy(storeQueue[store_idx].data, &gData, sizeof(T));
719
720 // This function only writes the data to the store queue, so no fault
721 // can happen here.
722 return NoFault;
723}
724
725#endif // __CPU_O3_LSQ_UNIT_HH__