1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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621 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %#x\n",
622 load_inst->seqNum, load_inst->readPC());
623
624 assert(!load_inst->memData);
625 load_inst->memData = new uint8_t[64];
626
627 ++usedPorts;
628
629 // if we the cache is not blocked, do cache access
630 if (!lsq->cacheBlocked()) {
631 PacketPtr data_pkt =
632 new Packet(req, Packet::ReadReq, Packet::Broadcast);
633 data_pkt->dataStatic(load_inst->memData);
634
635 LSQSenderState *state = new LSQSenderState;
636 state->isLoad = true;
637 state->idx = load_idx;
638 state->inst = load_inst;
639 data_pkt->senderState = state;
640
641 if (!dcachePort->sendTiming(data_pkt)) {
642 Packet::Result result = data_pkt->result;
643
644 // Delete state and data packet because a load retry
645 // initiates a pipeline restart; it does not retry.
646 delete state;
647 delete data_pkt;
648
649 if (result == Packet::BadAddress) {
650 return TheISA::genMachineCheckFault();
651 }
652
653 // If the access didn't succeed, tell the LSQ by setting
654 // the retry thread id.
655 lsq->setRetryTid(lsqID);
656 }
657 }

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671 // refetched, and re-executed.
672 isLoadBlocked = true;
673 loadBlockedHandled = false;
674 blockedLoadSeqNum = load_inst->seqNum;
675 // No fault occurred, even though the interface is blocked.
676 return NoFault;
677 }
678
679 return NoFault;
680}
681
682template <class Impl>
683template <class T>
684Fault
685LSQUnit<Impl>::write(Request *req, T &data, int store_idx)
686{

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