lsq_impl.hh (8707:489489c67fd9) lsq_impl.hh (8793:5f25086326ac)
1/*
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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47#include "cpu/o3/lsq.hh"
48#include "debug/Fetch.hh"
49#include "debug/LSQ.hh"
50#include "debug/Writeback.hh"
51#include "params/DerivO3CPU.hh"
52
53using namespace std;
54
2 * Copyright (c) 2005-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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35#include "cpu/o3/lsq.hh"
36#include "debug/Fetch.hh"
37#include "debug/LSQ.hh"
38#include "debug/Writeback.hh"
39#include "params/DerivO3CPU.hh"
40
41using namespace std;
42
43template<class Impl>
44void
45LSQ<Impl>::DcachePort::setPeer(Port *port)
46{
47 Port::setPeer(port);
48
49 // Update the ThreadContext's memory ports (Functional/Virtual
50 // Ports)
51 lsq->updateMemPorts();
52}
53
55template <class Impl>
54template <class Impl>
55Tick
56LSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
57{
58 panic("O3CPU model does not work with atomic mode!");
59 return curTick();
60}
61
62template <class Impl>
63void
64LSQ<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
65{
66 DPRINTF(LSQ, "LSQ doesn't update things on a recvFunctional.\n");
67}
68
69template <class Impl>
70void
71LSQ<Impl>::DcachePort::recvStatusChange(Status status)
72{
73 if (status == RangeChange) {
74 if (!snoopRangeSent) {
75 snoopRangeSent = true;
76 sendStatusChange(Port::RangeChange);
77 }
78 return;
79 }
80 panic("O3CPU doesn't expect recvStatusChange callback!");
81}
82
83template <class Impl>
84bool
85LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
86{
87 if (pkt->isError())
88 DPRINTF(LSQ, "Got error packet back for address: %#X\n", pkt->getAddr());
89 if (pkt->isResponse()) {
90 lsq->thread[pkt->req->threadId()].completeDataAccess(pkt);
91 } else {
92 DPRINTF(LSQ, "received pkt for addr:%#x %s\n", pkt->getAddr(),
93 pkt->cmdString());
94
95 // must be a snoop
96 if (pkt->isInvalidate()) {
97 DPRINTF(LSQ, "received invalidation for addr:%#x\n", pkt->getAddr());
98 for (ThreadID tid = 0; tid < lsq->numThreads; tid++) {
99 lsq->thread[tid].checkSnoop(pkt);
100 }
101 }
102 // to provide stronger consistency model
103 }
104 return true;
105}
106
107template <class Impl>
108void
109LSQ<Impl>::DcachePort::recvRetry()
110{
111 if (lsq->retryTid == -1)
112 {
113 //Squashed, so drop it
114 return;
115 }
116 int curr_retry_tid = lsq->retryTid;
117 // Speculatively clear the retry Tid. This will get set again if
118 // the LSQUnit was unable to complete its access.
119 lsq->retryTid = -1;
120 lsq->thread[curr_retry_tid].recvRetry();
121}
122
123template <class Impl>
56LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params)
124LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params)
57 : cpu(cpu_ptr), iewStage(iew_ptr),
125 : cpu(cpu_ptr), iewStage(iew_ptr), dcachePort(this),
58 LQEntries(params->LQEntries),
59 SQEntries(params->SQEntries),
60 numThreads(params->numThreads),
61 retryTid(-1)
62{
126 LQEntries(params->LQEntries),
127 SQEntries(params->SQEntries),
128 numThreads(params->numThreads),
129 retryTid(-1)
130{
131 dcachePort.snoopRangeSent = false;
132
63 //**********************************************/
64 //************ Handle SMT Parameters ***********/
65 //**********************************************/
66 std::string policy = params->smtLSQPolicy;
67
68 //Convert string to lowercase
69 std::transform(policy.begin(), policy.end(), policy.begin(),
70 (int(*)(int)) tolower);

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106 assert(0 && "Invalid LSQ Sharing Policy.Options Are:{Dynamic,"
107 "Partitioned, Threshold}");
108 }
109
110 //Initialize LSQs
111 for (ThreadID tid = 0; tid < numThreads; tid++) {
112 thread[tid].init(cpu, iew_ptr, params, this,
113 maxLQEntries, maxSQEntries, tid);
133 //**********************************************/
134 //************ Handle SMT Parameters ***********/
135 //**********************************************/
136 std::string policy = params->smtLSQPolicy;
137
138 //Convert string to lowercase
139 std::transform(policy.begin(), policy.end(), policy.begin(),
140 (int(*)(int)) tolower);

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176 assert(0 && "Invalid LSQ Sharing Policy.Options Are:{Dynamic,"
177 "Partitioned, Threshold}");
178 }
179
180 //Initialize LSQs
181 for (ThreadID tid = 0; tid < numThreads; tid++) {
182 thread[tid].init(cpu, iew_ptr, params, this,
183 maxLQEntries, maxSQEntries, tid);
114 thread[tid].setDcachePort(cpu_ptr->getDcachePort());
184 thread[tid].setDcachePort(&dcachePort);
115 }
116}
117
118
119template<class Impl>
120std::string
121LSQ<Impl>::name() const
122{

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296
297 if (thread[tid].violation())
298 return true;
299 }
300
301 return false;
302}
303
185 }
186}
187
188
189template<class Impl>
190std::string
191LSQ<Impl>::name() const
192{

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366
367 if (thread[tid].violation())
368 return true;
369 }
370
371 return false;
372}
373
304template <class Impl>
305void
306LSQ<Impl>::recvRetry()
307{
308 if (retryTid == InvalidThreadID)
309 {
310 //Squashed, so drop it
311 return;
312 }
313 int curr_retry_tid = retryTid;
314 // Speculatively clear the retry Tid. This will get set again if
315 // the LSQUnit was unable to complete its access.
316 retryTid = -1;
317 thread[curr_retry_tid].recvRetry();
318}
319
320template <class Impl>
321bool
322LSQ<Impl>::recvTiming(PacketPtr pkt)
323{
324 if (pkt->isError())
325 DPRINTF(LSQ, "Got error packet back for address: %#X\n",
326 pkt->getAddr());
327 if (pkt->isResponse()) {
328 thread[pkt->req->threadId()].completeDataAccess(pkt);
329 } else {
330 DPRINTF(LSQ, "received pkt for addr:%#x %s\n", pkt->getAddr(),
331 pkt->cmdString());
332
333 // must be a snoop
334 if (pkt->isInvalidate()) {
335 DPRINTF(LSQ, "received invalidation for addr:%#x\n",
336 pkt->getAddr());
337 for (ThreadID tid = 0; tid < numThreads; tid++) {
338 thread[tid].checkSnoop(pkt);
339 }
340 }
341 // to provide stronger consistency model
342 }
343 return true;
344}
345
346template<class Impl>
347int
348LSQ<Impl>::getCount()
349{
350 unsigned total = 0;
351
352 list<ThreadID>::iterator threads = activeThreads->begin();
353 list<ThreadID>::iterator end = activeThreads->end();

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375int
376LSQ<Impl>::getCount()
377{
378 unsigned total = 0;
379
380 list<ThreadID>::iterator threads = activeThreads->begin();
381 list<ThreadID>::iterator end = activeThreads->end();

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