lsq_impl.hh (8706:b1838faf3bcc) | lsq_impl.hh (8707:489489c67fd9) |
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1/* | 1/* |
2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * |
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2 * Copyright (c) 2005-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright --- 26 unchanged lines hidden (view full) --- 36#include "debug/Fetch.hh" 37#include "debug/LSQ.hh" 38#include "debug/Writeback.hh" 39#include "params/DerivO3CPU.hh" 40 41using namespace std; 42 43template <class Impl> | 14 * Copyright (c) 2005-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright --- 26 unchanged lines hidden (view full) --- 48#include "debug/Fetch.hh" 49#include "debug/LSQ.hh" 50#include "debug/Writeback.hh" 51#include "params/DerivO3CPU.hh" 52 53using namespace std; 54 55template <class Impl> |
44Tick 45LSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt) 46{ 47 panic("O3CPU model does not work with atomic mode!"); 48 return curTick(); 49} 50 51template <class Impl> 52void 53LSQ<Impl>::DcachePort::recvFunctional(PacketPtr pkt) 54{ 55 DPRINTF(LSQ, "LSQ doesn't update things on a recvFunctional.\n"); 56} 57 58template <class Impl> 59void 60LSQ<Impl>::DcachePort::recvStatusChange(Status status) 61{ 62 if (status == RangeChange) { 63 if (!snoopRangeSent) { 64 snoopRangeSent = true; 65 sendStatusChange(Port::RangeChange); 66 } 67 return; 68 } 69 panic("O3CPU doesn't expect recvStatusChange callback!"); 70} 71 72template <class Impl> 73bool 74LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt) 75{ 76 if (pkt->isError()) 77 DPRINTF(LSQ, "Got error packet back for address: %#X\n", pkt->getAddr()); 78 if (pkt->isResponse()) { 79 lsq->thread[pkt->req->threadId()].completeDataAccess(pkt); 80 } else { 81 DPRINTF(LSQ, "received pkt for addr:%#x %s\n", pkt->getAddr(), 82 pkt->cmdString()); 83 84 // must be a snoop 85 if (pkt->isInvalidate()) { 86 DPRINTF(LSQ, "received invalidation for addr:%#x\n", pkt->getAddr()); 87 for (ThreadID tid = 0; tid < lsq->numThreads; tid++) { 88 lsq->thread[tid].checkSnoop(pkt); 89 } 90 } 91 // to provide stronger consistency model 92 } 93 return true; 94} 95 96template <class Impl> 97void 98LSQ<Impl>::DcachePort::recvRetry() 99{ 100 if (lsq->retryTid == -1) 101 { 102 //Squashed, so drop it 103 return; 104 } 105 int curr_retry_tid = lsq->retryTid; 106 // Speculatively clear the retry Tid. This will get set again if 107 // the LSQUnit was unable to complete its access. 108 lsq->retryTid = -1; 109 lsq->thread[curr_retry_tid].recvRetry(); 110} 111 112template <class Impl> | |
113LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params) | 56LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params) |
114 : cpu(cpu_ptr), iewStage(iew_ptr), dcachePort(this), | 57 : cpu(cpu_ptr), iewStage(iew_ptr), |
115 LQEntries(params->LQEntries), 116 SQEntries(params->SQEntries), 117 numThreads(params->numThreads), 118 retryTid(-1) 119{ | 58 LQEntries(params->LQEntries), 59 SQEntries(params->SQEntries), 60 numThreads(params->numThreads), 61 retryTid(-1) 62{ |
120 dcachePort.snoopRangeSent = false; 121 | |
122 //**********************************************/ 123 //************ Handle SMT Parameters ***********/ 124 //**********************************************/ 125 std::string policy = params->smtLSQPolicy; 126 127 //Convert string to lowercase 128 std::transform(policy.begin(), policy.end(), policy.begin(), 129 (int(*)(int)) tolower); --- 35 unchanged lines hidden (view full) --- 165 assert(0 && "Invalid LSQ Sharing Policy.Options Are:{Dynamic," 166 "Partitioned, Threshold}"); 167 } 168 169 //Initialize LSQs 170 for (ThreadID tid = 0; tid < numThreads; tid++) { 171 thread[tid].init(cpu, iew_ptr, params, this, 172 maxLQEntries, maxSQEntries, tid); | 63 //**********************************************/ 64 //************ Handle SMT Parameters ***********/ 65 //**********************************************/ 66 std::string policy = params->smtLSQPolicy; 67 68 //Convert string to lowercase 69 std::transform(policy.begin(), policy.end(), policy.begin(), 70 (int(*)(int)) tolower); --- 35 unchanged lines hidden (view full) --- 106 assert(0 && "Invalid LSQ Sharing Policy.Options Are:{Dynamic," 107 "Partitioned, Threshold}"); 108 } 109 110 //Initialize LSQs 111 for (ThreadID tid = 0; tid < numThreads; tid++) { 112 thread[tid].init(cpu, iew_ptr, params, this, 113 maxLQEntries, maxSQEntries, tid); |
173 thread[tid].setDcachePort(&dcachePort); | 114 thread[tid].setDcachePort(cpu_ptr->getDcachePort()); |
174 } 175} 176 177 178template<class Impl> 179std::string 180LSQ<Impl>::name() const 181{ --- 173 unchanged lines hidden (view full) --- 355 356 if (thread[tid].violation()) 357 return true; 358 } 359 360 return false; 361} 362 | 115 } 116} 117 118 119template<class Impl> 120std::string 121LSQ<Impl>::name() const 122{ --- 173 unchanged lines hidden (view full) --- 296 297 if (thread[tid].violation()) 298 return true; 299 } 300 301 return false; 302} 303 |
304template <class Impl> 305void 306LSQ<Impl>::recvRetry() 307{ 308 if (retryTid == InvalidThreadID) 309 { 310 //Squashed, so drop it 311 return; 312 } 313 int curr_retry_tid = retryTid; 314 // Speculatively clear the retry Tid. This will get set again if 315 // the LSQUnit was unable to complete its access. 316 retryTid = -1; 317 thread[curr_retry_tid].recvRetry(); 318} 319 320template <class Impl> 321bool 322LSQ<Impl>::recvTiming(PacketPtr pkt) 323{ 324 if (pkt->isError()) 325 DPRINTF(LSQ, "Got error packet back for address: %#X\n", 326 pkt->getAddr()); 327 if (pkt->isResponse()) { 328 thread[pkt->req->threadId()].completeDataAccess(pkt); 329 } else { 330 DPRINTF(LSQ, "received pkt for addr:%#x %s\n", pkt->getAddr(), 331 pkt->cmdString()); 332 333 // must be a snoop 334 if (pkt->isInvalidate()) { 335 DPRINTF(LSQ, "received invalidation for addr:%#x\n", 336 pkt->getAddr()); 337 for (ThreadID tid = 0; tid < numThreads; tid++) { 338 thread[tid].checkSnoop(pkt); 339 } 340 } 341 // to provide stronger consistency model 342 } 343 return true; 344} 345 |
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363template<class Impl> 364int 365LSQ<Impl>::getCount() 366{ 367 unsigned total = 0; 368 369 list<ThreadID>::iterator threads = activeThreads->begin(); 370 list<ThreadID>::iterator end = activeThreads->end(); --- 253 unchanged lines hidden --- | 346template<class Impl> 347int 348LSQ<Impl>::getCount() 349{ 350 unsigned total = 0; 351 352 list<ThreadID>::iterator threads = activeThreads->begin(); 353 list<ThreadID>::iterator end = activeThreads->end(); --- 253 unchanged lines hidden --- |